公开(公告)号：US08017464B2

公开(公告)日：2011-09-13

申请号：US12558498

申请日：2009-09-12

申请人： Masao Sugiyama ,  Yoshiyuki Kaneko ,  Yoshinori Kondo ,  Masayoshi Hirasawa

发明人： Masao Sugiyama ,  Yoshiyuki Kaneko ,  Yoshinori Kondo ,  Masayoshi Hirasawa

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/28518 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76819 ,  H01L23/485 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： As a method for constituting a pre-metal interlayer insulating film, such method is considered as forming a CVD silicon oxide-based insulating film having good filling properties of a silicon oxide film by ozone TEOS, reflowing the film at high temperatures to planarize it, then stacking a silicon oxide film having good CMP scratch resistance by plasma TEOS, and, further, planarizing it by CMP. However, it was made clear that, in a process for forming a contact hole, crack in the pre-metal interlayer insulating film is exposed in the contact hole, into which barrier metal intrudes to cause short-circuit defects.In the present invention, in the pre-metal process, after forming the ozone TEOS film over an etch stop film, the ozone TEOS film is once etched back so as to expose the etch stop film over a gate structure, and, after that, a plasma TEOS film is formed over the remaining ozone TEOS film, and then the plasma TEOS film is planarized by CMP.

摘要翻译： 作为构成前金属层间绝缘膜的方法，认为通过臭氧TEOS形成氧化硅膜的填充性良好的CVD硅氧化物类绝缘膜，在高温下回流以使其平坦化， 然后通过等离子体TEOS层叠具有良好CMP耐刮擦性的氧化硅膜，并且进一步通过CMP对其进行平坦化。 但是，在形成接触孔的工序中，在金属间绝缘膜的裂纹暴露在接触孔内，阻挡金属侵入其中而引起短路缺陷。 在本发明中，在预金属工艺中，在蚀刻停止膜上形成臭氧TEOS膜之后，臭氧TEOS膜被一次回蚀刻，以便在栅极结构上暴露蚀刻停止膜，之后， 在剩余的臭氧TEOS膜上形成等离子体TEOS膜，然后通过CMP平坦化等离子体TEOS膜。

公开(公告)号：US20090179247A1

公开(公告)日：2009-07-16

申请号：US12354254

申请日：2009-01-15

申请人： Masako FUJII ,  Shigeki Obayashi ,  Naozumi Morino ,  Atsushi Hiraiwa ,  Shinichi Watarai ,  Takeshi Yoshida ,  Kazutoshi Oku ,  Masao Sugiyama ,  Yoshinori Kondo ,  Yuichi Egawa ,  Yoshiyuki Kaneko

发明人： Masako FUJII ,  Shigeki Obayashi ,  Naozumi Morino ,  Atsushi Hiraiwa ,  Shinichi Watarai ,  Takeshi Yoshida ,  Kazutoshi Oku ,  Masao Sugiyama ,  Yoshinori Kondo ,  Yuichi Egawa ,  Yoshiyuki Kaneko

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L21/823892 ,  H01L27/092

摘要： A technique which can improve manufacturing yield and product reliability is provided in a semiconductor device having a triple well structure. An inverter circuit which includes an n-channel type field effect transistor formed in a shallow p-type well and a p-channel type field effect transistor formed in a shallow n-type well, and does not contribute to circuit operations is provided in a deep n-type well formed in a p-type substrate; the shallow p-type well is connected to the substrate using a wiring of a first layer; and the gate electrode of the p-channel type field effect transistor and the gate electrode of the n-channel type field effect transistor are connected to the shallow n-type well using a wiring of an uppermost layer.

摘要翻译： 在具有三重阱结构的半导体器件中提供了可以提高制造成品率和产品可靠性的技术。 形成在浅p型阱中的n沟道型场效应晶体管和形成在浅n型阱中的p沟道型场效应晶体管并且对电路操作无贡献的逆变器电路设置在 在p型衬底中形成深n型阱; 使用第一层的布线将浅的p型阱连接到基板; 并且p沟道型场效应晶体管的栅电极和n沟道型场效应晶体管的栅电极使用最上层的布线连接到浅n型阱。

公开(公告)号：US06800428B2

公开(公告)日：2004-10-05

申请号：US10133590

申请日：2002-04-29

申请人： Tomoyuki Okada ,  Taketoshi Omata ,  Kazuya Sugawa ,  Kiyokazu Aiso ,  Masao Sugiyama ,  Tomoaki Kawaguchi

发明人： Tomoyuki Okada ,  Taketoshi Omata ,  Kazuya Sugawa ,  Kiyokazu Aiso ,  Masao Sugiyama ,  Tomoaki Kawaguchi

IPC分类号： G03F700

CPC分类号： G03F1/50 ,  G03F7/70466

摘要： A method of generating an exposure pattern for lithography to create a plurality of patterns arranged in a predetermined direction, comprises a step of counting the plurality of patterns along this predetermined direction, and generating a first enlarged pattern by moving the edges to a first direction along the predetermined direction for a pattern with an odd number, and by moving the edges to a second direction, which is opposite to the first direction, for a pattern with an even number, and a step of generating a second enlarged pattern by moving the edges to the second direction for the pattern with an odd number, and by moving the edges to the first direction for the pattern with an even number. And the first and second patterns are used for creating the plurality of original patterns in a lithography step using the respective enlarged patterns.

摘要翻译： 一种产生用于光刻的曝光图案以产生沿预定方向布置的多个图案的方法，包括沿着该预定方向对多个图案进行计数的步骤，并且通过沿着第一方向移动边缘来产生第一放大图案 对于具有奇数的图案的预定方向，以及通过将与第一方向相反的第二方向移动到具有偶数的图案的第二方向，以及通过使边缘移动来产生第二放大图案的步骤 到具有奇数的图案的第二方向，并且通过将边缘移动到具有偶数的图案的第一方向。 并且第一和第二图案用于使用各自的放大图案在光刻步骤中创建多个原始图案。

公开(公告)号：US06421932B2

公开(公告)日：2002-07-23

申请号：US09780498

申请日：2001-02-12

申请人： Kazuhiko Gommori ,  Kazuto Kinoshita ,  Isamu Akiba ,  Masao Sugiyama

发明人： Kazuhiko Gommori ,  Kazuto Kinoshita ,  Isamu Akiba ,  Masao Sugiyama

IPC分类号： F26B300

CPC分类号： F26B5/14 ,  F26B15/12 ,  F26B21/004

摘要： While being transferred in substantially horizontal state along a predetermined path of transfer by a conveyer means, a substrate plate is dried by a jet of compressed air which is spurted out from a slit-like mouth of an air knife nozzle crosswise of the entire width of the substrate plate and at a predetermined angle of incidence with respect to a drying surface of the substrate plate to scrape off a liquid. The angle of incidence of jet air is made shallower as soon as the substrate on the conveyer means comes to a point of entry to an air blasting zone and is made deeper at latest when the substrate plate comes to a position immediately before a point of disengagement from the air blasting zone.

摘要翻译： 当沿着预定的传送路径以大致水平的状态转移时，通过压缩空气的喷射流干燥衬底板，压缩空气从空气刀喷嘴的狭缝状口喷出，横截面为整个宽度 并且相对于基板的干燥表面以预定的入射角度刮去液体。 一旦输送装置上的基板进入到喷气区，喷射空气的入射角变得更浅，并且当基板刚刚脱离接合点之前立即变得更深 从喷砂区。

公开(公告)号：US6165878A

公开(公告)日：2000-12-26

申请号：US221128

申请日：1998-12-28

申请人： Hideyo Haruhana ,  Keiichi Higashitani ,  Motoshige Igarashi ,  Masao Sugiyama

发明人： Hideyo Haruhana ,  Keiichi Higashitani ,  Motoshige Igarashi ,  Masao Sugiyama

IPC分类号： H01L21/28 ,  H01L21/027 ,  H01L21/31 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/027 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76832

摘要： A method of manufacturing a semiconductor device which prevents a short circuit between a gate electrode and a diffusion layer region if a contact hole is shifted from its proper position. A material having an etch selectivity to an interlayer insulation film is formed over the gate electrode to serve as a cover against the formation of a contact hole. A material is not formed over an interconnect line which is required to be exposed to a contact hole.

摘要翻译： 一种制造半导体器件的方法，如果接触孔从其正确的位置偏移，则可以防止栅电极和扩散层区域之间的短路。 在栅电极上形成具有对层间绝缘膜的蚀刻选择性的材料，以作为防止形成接触孔的盖。 不需要在暴露于接触孔的互连线上形成材料。

公开(公告)号：US08110878B2

公开(公告)日：2012-02-07

申请号：US13179163

申请日：2011-07-08

申请人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US07982271B2

公开(公告)日：2011-07-19

申请号：US12901858

申请日：2010-10-11

申请人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

发明人： Naozumi Morino ,  Atsushi Hiraiwa ,  Kazutoshi Oku ,  Toshiaki Ito ,  Motoshige Igarashi ,  Takayuki Sasaki ,  Masao Sugiyama ,  Hiroshi Yanagita ,  Shinichi Watarai

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/62

CPC分类号： H01L21/823892 ,  H01L27/0629 ,  H01L27/0928 ,  H01L2224/05554

摘要： There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

摘要翻译： 提供了一种在具有三重阱结构的半导体器件中提高制造产量和产品可靠性的技术。 在形成深n型阱，浅P型阱和浅n型阱的p型衬底中，在与各个区域不同的区域中形成浅的p型阱。 形成在浅p型阱中的p型扩散抽头使用在第二层中的互连在深n型阱中连接到形成在浅n型阱中的p型扩散阱。 每个形成在深n型阱中的nMIS和pMIS的相应栅极电极使用在第二层或更高级层中的互连而在衬底中形成的nMIS和pMIS的相应漏电极耦合。

公开(公告)号：US06545771B1

公开(公告)日：2003-04-08

申请号：US09388933

申请日：1999-09-02

申请人： Yoichi Sakai ,  Masao Sugiyama

发明人： Yoichi Sakai ,  Masao Sugiyama

IPC分类号： G06K1500

CPC分类号： H04N1/32133

摘要： An object of the present invention is to discriminate received information from one and same originator visually and readily. A CPU detects identification information of the originator in receiving a facsimile. It also selects identification information which coincides with the identification information detected among identification information of originators stored in a printing color table in a RAM in advance and selects a printing color corresponding to the identification information. A signal generating circuit generates an index signal which instructs to print an index mark in a selected printing color. The CPU controls an operation of a color printer so as to print the index mark in a predetermined color based on the index signal together with image information. It is possible to discriminate information transmitted from a predetermined terminal by selecting the recording sheet on which the index mark of the predetermined printing color is printed out of the mixed recording sheets. The recording sheet may be readily selected visually because the information is distinguished by the colors.

摘要翻译： 本发明的目的是从视觉上和容易地识别接收到的信息与一个和相同的发起者。 CPU在接收传真时检测发信人的识别信息。 它还预先选择与存储在RAM中的打印色表中的始发者的识别信息中检测到的识别信息一致的识别信息，并选择与识别信息相对应的打印颜色。 信号发生电路产生指示以所选择的打印颜色打印索引标记的索引信号。 CPU控制彩色打印机的操作，以便根据索引信号和图像信息，以预定颜色打印索引标记。 通过从混合记录纸中选择其上打印有预定打印色的索引标记的记录纸，可以区分从预定终端发送的信息。 记录纸可以容易地被视觉地选择，因为信息被颜色区分开。

公开(公告)号：US06344697B2

公开(公告)日：2002-02-05

申请号：US09197765

申请日：1998-11-23

申请人： Masao Sugiyama

发明人： Masao Sugiyama

IPC分类号： H01L23544

CPC分类号： H01L23/544 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A semiconductor device that permits effective use of a region positioned under a positional detection mark or an external electrode, i.e., the region that has not been conventionally utilized may be provided. In a semiconductor device including a lower layer, a shielding film and an upper layer, the lower layer includes at least one selected from the group consisting of a positional detection mark, a quality testing element, and a circuit element. The shielding film is formed on the lower layer and shields an energy beam used for detecting a positional detection mark. The upper layer includes a positional detection mark formed on the shielding film.

摘要翻译： 可以提供允许有效利用位于位置检测标记或外部电极即未经常使用的区域的区域的半导体器件。 在包括下层，屏蔽膜和上层的半导体器件中，下层包括从由位置检测标记，质量检测元件和电路元件组成的组中选择的至少一种。 屏蔽膜形成在下层上并屏蔽用于检测位置检测标记的能量束。 上层包括形成在屏蔽膜上的位置检测标记。

公开(公告)号：US5600170A

公开(公告)日：1997-02-04

申请号：US479735

申请日：1995-06-07

申请人： Masao Sugiyama ,  Hiroyuki Amishiro ,  Keiichi Higashitani

发明人： Masao Sugiyama ,  Hiroyuki Amishiro ,  Keiichi Higashitani

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L23/485 ,  H01L21/768 ,  H01L21/76895 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/49 ,  H01L2924/0002

摘要： An interconnection structure of a semiconductor device with a gate electrode, an active region provided in the vicinity of the gate electrode and a first buried layer in a contact hole exposing the gate electrode and the active region. The contact hole is easily formed, and the first buried layer has a substantially low interconnection resistance value.

摘要翻译： 具有栅电极的半导体器件的互连结构，设置在栅电极附近的有源区和露出栅电极和有源区的接触孔中的第一掩埋层。 接触孔容易形成，并且第一掩埋层具有基本上较低的互连电阻值。