公开(公告)号：US09899261B2

公开(公告)日：2018-02-20

申请号：US15365394

申请日：2016-11-30

Applicant: MediaTek Inc.

Inventor： Cheng-Chou Hung ,  Ming-Tzong Yang ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L29/06 ,  H01L21/761 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/761 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L29/0619 ,  H01L29/0623 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.

公开(公告)号：US20150001675A1

公开(公告)日：2015-01-01

申请号：US14490690

申请日：2014-09-19

Applicant: MEDIATEK INC.

Inventor： Tien-Chang Chang ,  Ming-Tzong Yang ,  Tao Cheng ,  Cheng-Hsing Chien ,  Hsin-Hsin Hsiao

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0811 ,  H01L29/94

Abstract: A semiconductor circuit comprises a first and a second logic circuit, a first and a second decoupling capacitor. The first decoupling capacitor is arranged in a first area around the first logic circuit and the second decoupling capacitor is arranged in a second area around the second logic circuit. Wherein, the first area is larger than the second area, a gate oxide thickness of the first decoupling capacitor is larger than a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit. Further, the first and second decoupling capacitors are designed without trench.

Abstract translation: 半导体电路包括第一和第二逻辑电路，第一和第二去耦电容器。 第一去耦电容器布置在第一逻辑电路周围的第一区域中，并且第二去耦电容器布置在第二逻辑电路周围的第二区域中。 其中，第一区域大于第二区域，第一去耦电容器的栅极氧化物厚度大于第二去耦电容器的栅极氧化物厚度，并且第一区域和第一逻辑电路之间的距离短于第 第二区域与第二逻辑电路之间的距离。 此外，第一和第二去耦电容器被设计成没有沟槽。

公开(公告)号：US20140199818A1

公开(公告)日：2014-07-17

申请号：US14218991

申请日：2014-03-19

Applicant: MEDIATEK INC.

Inventor： Ming-Tzong Yang ,  Ming-Cheng Lee

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66477 ,  H01L21/265 ,  H01L21/823418 ,  H01L21/823814 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/78612

Abstract: A method for fabricating an ESD protection device . Agate electrode of a core device is formed in a non I/O region and a gate electrode of an ESD protection device is formed in a I/O region. A first photoresist film masks the I/O region and reveals the non I/O region. The first photoresist film includes at least an opening adjacent to the gate electrode of the ESD protection device in the I/O region. A core pocket implantation process using the first photoresist film as an implant mask is performed to implant dopants of a second conductivity type into the I/O region through the opening and into the non I/O region, thereby forming a core pocket doping region in the I/O region and core pocket doping regions in the non I/O region.

Abstract translation: 一种制造ESD保护装置的方法。 核心器件的玛瑙电极形成在非I / O区域中，并且ESD保护器件的栅电极形成在I / O区域中。 第一光致抗蚀剂膜掩蔽I / O区域并显露非I / O区域。 第一光致抗蚀剂膜包括与I / O区域中的ESD保护装置的栅电极相邻的至少一个开口。 执行使用第一光致抗蚀剂膜作为注入掩模的核心袋注入工艺，以将第二导电类型的掺杂剂通过开口注入I / O区域并进入非I / O区域，由此形成核心袋掺杂区域 非I / O区域中的I / O区域和核心袋掺杂区域。

公开(公告)号：US20220059429A1

公开(公告)日：2022-02-24

申请号：US17133896

申请日：2020-12-24

Applicant: Chee-Wee LIU ,  MEDIATEK INC.

Inventor： Ming-Tzong Yang ,  Hsien-Hsin Lin ,  Wen-Kai Wan ,  Chia-Che Chung ,  Chee-Wee Liu

IPC: H01L23/373 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm−1K−1and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor.

公开(公告)号：US09870980B2

公开(公告)日：2018-01-16

申请号：US14986295

申请日：2015-12-31

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Yu-Hua Huang ,  Wei-Che Huang

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L23/5384 ,  H01L24/11 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42356 ,  H01L2224/02372 ,  H01L2224/0912 ,  H01L2225/06541

Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure.

公开(公告)号：US09548289B2

公开(公告)日：2017-01-17

申请号：US14741796

申请日：2015-06-17

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Ming-Tzong Yang

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/34 ,  H01L25/18 ,  H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/50 ,  H01L23/00 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/50 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/10 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H05K1/112 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. First vias are disposed on the first semiconductor die, coupled to the first pads. A first dynamic random access memory (DRAM) die is mounted on the first semiconductor die, coupled to the first vias. A second semiconductor package is stacked on the first semiconductor package. The second semiconductor package includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface. A second dynamic random access memory (DRAM) die is mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first DRAM die is different from the number of input/output (I/O) pins of the second DRAM die.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括第一半导体封装。 第一半导体封装包括其上具有第一焊盘的第一半导体管芯。 第一通孔设置在第一半导体管芯上，耦合到第一焊盘。 第一动态随机存取存储器（DRAM）管芯安装在第一半导体管芯上，耦合到第一通孔。 第二半导体封装堆叠在第一半导体封装上。 第二半导体封装包括具有管芯附接表面和与管芯附接表面相对的凸起附着表面的主体。 第二动态随机存取存储器（DRAM）裸片安装在芯片附接表面上，通过接合线耦合到主体。 第一DRAM裸片的输入/输出（I / O）引脚的数量与第二DRAM裸片的输入/输出（I / O）引脚的数量不同。

公开(公告)号：US20150091158A1

公开(公告)日：2015-04-02

申请号：US14040732

申请日：2013-09-30

Applicant: MEDIATEK INC.

Inventor： Tzu-Hung Lin ,  Yu-Hua Huang ,  Wei-Che Huang ,  Ming-Tzong Yang

IPC: H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/32014 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A package structure, comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die to the second die such that the first die and the second die are electrically connected; and at least one bonding wire, for electrically connecting the first die to the conductive units or the substrate.

Abstract translation: 一种封装结构，包括：衬底，其具有设置在所述衬底的第一表面处的至少一个导电单元; 至少一个第一管芯，设置在所述衬底的第二表面上; 连接层; 设置在所述连接层上的第二管芯，其中所述连接层包括用于将所述第一管芯连接到所述第二管芯的至少一个突起，使得所述第一管芯和所述第二管芯电连接; 以及用于将第一管芯电连接到导电单元或基板的至少一个接合线。

公开(公告)号：US08987851B2

公开(公告)日：2015-03-24

申请号：US13790060

申请日：2013-03-08

Applicant: MediaTek Inc.

Inventor： Ming-Tzong Yang ,  Cheng-Chou Hung ,  Tung-Hsing Lee ,  Wei-Che Huang ,  Yu-Hua Huang

IPC: H01L27/14 ,  H01L29/40 ,  H01L21/76 ,  H01L23/522 ,  H01L31/18 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/02107 ,  H01L21/268 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L31/18 ,  H01L2223/6616 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/11 ,  H01L2924/12042 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention provides a radio-frequency (RF) device package and a method for fabricating the same. An exemplary embodiment of a radio-frequency (RF) device package includes a base, wherein a radio-frequency (RF) device chip is mounted on the base. The RF device chip includes a semiconductor substrate having a front side and a back side. A radio-frequency (RF) component is disposed on the front side of the semiconductor substrate. An interconnect structure is disposed on the RF component, wherein the interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. A through hole is formed through the semiconductor substrate from the back side of the semiconductor substrate, and is connected to the interconnect structure. A TSV structure is disposed in the through hole.

Abstract translation: 本发明提供一种射频（RF）器件封装及其制造方法。 射频（RF）器件封装的示例性实施例包括基座，其中射频（RF）器件芯片安装在基座上。 RF器件芯片包括具有前侧和后侧的半导体衬底。 射频（RF）部件设置在半导体衬底的前侧。 互连结构设置在RF部件上，其中互连结构电连接到RF部件，并且半导体衬底的厚度小于互连结构的厚度。 从半导体衬底的背面穿过半导体衬底形成一个通孔，并连接到互连结构。 TSV结构设置在通孔中。

公开(公告)号：US11587846B2

公开(公告)日：2023-02-21

申请号：US17133896

申请日：2020-12-24

Applicant: MEDIATEK INC. ,  Chee-Wee Liu

Inventor： Ming-Tzong Yang ,  Hsien-Hsin Lin ,  Wen-Kai Wan ,  Chia-Che Chung ,  Chee-Wee Liu

IPC: H01L23/373 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a heat dissipation substrate and a device layer. The thermal conductivity of the heat dissipation substrate is greater than 200 Wm−1K−1 and the device layer is disposed on the heat dissipation substrate. The device layer includes a transistor. A method of forming a semiconductor device includes providing a base substrate, forming a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is greater than 200 Wm−1K−1. The method further includes forming a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further includes removing the base substrate.

公开(公告)号：US20200303352A1

公开(公告)日：2020-09-24

申请号：US16899335

申请日：2020-06-11

Applicant: MediaTek Inc.

Inventor： Tzu-Hung Lin ,  Yu-Hua Huang ,  Wei-Che Huang ,  Ming-Tzong Yang

IPC: H01L25/065 ,  H01L23/00

Abstract: A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.