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    METHODS FOR DEVICE FABRICATION USING PITCH REDUCTION AND RELATED DEVICES
    11.
    发明申请
    METHODS FOR DEVICE FABRICATION USING PITCH REDUCTION AND RELATED DEVICES 审中-公开
    用于减少装置的装置制造方法和相关装置

    公开(公告)号：US20150170905A1

    公开(公告)日：2015-06-18

    申请号：US14635023

    申请日：2015-03-02

    Applicant: Micron Technology, Inc.

    Inventor： Luan C. Tran ,  Raghupathy Giridhar

    IPC: H01L21/027 ,  H01L21/311 ,  H01L27/105 ,  H01L21/033

    CPC classification number: H01L21/0274 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/1052

    Abstract: Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.

    Abstract translation: 用于通过反向间距减小流程进行器件制造的方法的实施例包括在形成第一特征图案之后形成衬底上方的特征的第一图案并形成间距倍数间隔物的第二图案。 在本发明的实施例中，可以通过光刻形成第一特征图案，并且可以通过间距倍增形成间距倍增间隔物的第二图案。 提供了其他用于器件制造的方法。

    MEMORY HAVING A CONTINUOUS CHANNEL
    14.
    发明申请
    MEMORY HAVING A CONTINUOUS CHANNEL 有权

    公开(公告)号：US20220238543A1

    公开(公告)日：2022-07-28

    申请号：US17723716

    申请日：2022-04-19

    Applicant: Micron Technology, Inc.

    Inventor： Luan C. Tran ,  Hongbin Zhu ,  John D. Hopkins ,  Yushi Hu

    IPC: H01L27/11556 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

    Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

    Drain select gate formation methods and apparatus
    16.
    发明授权
    Drain select gate formation methods and apparatus 有权

    公开(公告)号：US10242995B2

    公开(公告)日：2019-03-26

    申请号：US15808468

    申请日：2017-11-09

    Applicant: Micron Technology, Inc.

    Inventor： Hongbin Zhu ,  Lijing Gou ,  Gordon Haller ,  Luan C. Tran

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/3205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/302

    Abstract: Some embodiments include a string of charge storage devices formed along a vertical channel of semiconductor material; a gate region of a drain select gate (SGD) transistor, the gate region at least partially surrounding the vertical channel; a dielectric barrier formed in the gate region; a first isolation layer formed above the gate region and the dielectric barrier; a drain region of the SGD transistor formed above the vertical channel; and a second isolation layer formed above the first isolation layer and the drain region, wherein the second isolation layer includes a conductive contact in electrical contact with the drain region of the SGD transistor. Additional apparatus and methods are disclosed.

    Integrated structures and methods of forming integrated structures
    18.
    发明授权
    Integrated structures and methods of forming integrated structures 有权

    公开(公告)号：US09773805B1

    公开(公告)日：2017-09-26

    申请号：US15187632

    申请日：2016-06-20

    Applicant: Micron Technology, Inc.

    Inventor： Jie Li ,  James Mathew ,  Kunal Shrotri ,  Luan C. Tran ,  Gordon A. Haller ,  Yangda Zhang ,  Hongpeng Yu ,  Minsoo Lee

    IPC: H01L29/51 ,  H01L27/11582 ,  H01L27/11556

    CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    Abstract: Some embodiments include an integrated structure having a first opening extending through a stack of alternating insulative levels and conductive levels. A nitride structure is within the first opening and narrows the first opening to form a second opening. Detectable oxide is between the nitride structure and one or more of the conductive levels. Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. A first opening extends through the vertically-stacked levels to the conductive material and has opposing sidewalls along a cross-section. Nitride liners are along the sidewalls of the first opening. Detectable oxide is between at least one of the nitride liners and one or more of the vertically-stacked conductive levels. Some embodiments include methods for forming integrated structures.

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