公开(公告)号：US20190206856A1

公开(公告)日：2019-07-04

申请号：US15892625

申请日：2018-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Smith ,  Kenneth W. Marr

IPC: H01L27/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/06 ,  H01L27/11526 ,  H01L27/11573 ,  G11C16/22

CPC classification number: H01L27/0266 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/22 ,  G11C16/26 ,  H01L21/28035 ,  H01L21/28158 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32137 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/0649

Abstract: Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

公开(公告)号：US09911692B2

公开(公告)日：2018-03-06

申请号：US15393553

申请日：2016-12-29

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Eric H. Freeman

IPC: H01L23/00 ,  H01L23/522 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

公开(公告)号：US20170025348A1

公开(公告)日：2017-01-26

申请号：US15288522

申请日：2016-10-07

Applicant: Micron Technology, Inc.

Inventor： Eric H. Freeman ,  Michael A. Smith

IPC: H01L23/528 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/311 ,  H01L27/115

CPC classification number: H01L23/528 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76892 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

Abstract translation: 公开了用于形成半导体结构的方法，包括形成导电材料和绝缘材料组的方法，在组上形成第一掩模，形成第一数量的接触区域，在组的第一区域上形成第二掩模， 以及在与所述第一区域横向相邻的第二暴露区域中从所述组中移除材料以形成第二数量的接触区域。 另一种方法包括在导电材料和绝缘材料组的部分上形成第一和第二接触区域，每个第二接触区域比每个第一接触区域更靠近下面的衬底。 还公开了诸如包括横向相邻的第一和第二区域的存储器件的装置，每个区域包括多个导电材料的不同部分的接触区域和形成这种器件的相关方法。

公开(公告)号：US20160099305A1

公开(公告)日：2016-04-07

申请号：US14966927

申请日：2015-12-11

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/06 ,  H01L29/788 ,  H01L29/78 ,  H01L27/115 ,  H01L29/66 ,  H01L29/08 ,  H01L27/02 ,  H01L29/792 ,  H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/085 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

公开(公告)号：US08999844B2

公开(公告)日：2015-04-07

申请号：US14015696

申请日：2013-08-30

Applicant: Micron Technology, Inc.

Inventor： Eric H. Freeman ,  Michael A. Smith

IPC: H01L21/44 ,  H01L21/461 ,  H01L29/76 ,  H01L21/302 ,  H01L21/822 ,  H01L21/768 ,  H01L27/115 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76892 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

Abstract translation: 公开了用于形成半导体结构的方法，包括形成导电材料和绝缘材料组的方法，在组上形成第一掩模，形成第一数量的接触区域，在组的第一区域上形成第二掩模， 以及在与所述第一区域横向相邻的第二暴露区域中从所述组中移除材料以形成第二数量的接触区域。 另一种方法包括在导电材料和绝缘材料组的部分上形成第一和第二接触区域，每个第二接触区域比每个第一接触区域更靠近下面的衬底。 还公开了诸如包括横向相邻的第一和第二区域的存储器件的装置，每个区域包括多个导电材料的不同部分的接触区域和形成这种器件的相关方法。

公开(公告)号：US20140339650A1

公开(公告)日：2014-11-20

申请号：US13897112

申请日：2013-05-17

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L29/10 ,  H01L29/78

CPC classification number: H01L29/1033 ,  H01L29/0653 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7835

Abstract: Some embodiments include transistors having a channel region under a gate, having a source/drain region laterally spaced from the channel region by an active region, and having one or more dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region. The dielectric features may be spaced-apart islands in some configurations. The dielectric features may be multi-branched interlocking structures in some configurations.

Abstract translation: 一些实施例包括在栅极下方具有沟道区的晶体管，其源极/漏极区域与沟道区域横向间隔有效区域，并且具有延伸穿过有源区域的一个或多个介电特征，排除了任何直线 从沟道区到源极/漏极区的横向导电路径。 在一些配置中，电介质特征可以是间隔开的岛。 介电特征可以是一些配置中的多分支互锁结构。

公开(公告)号：US20140300006A1

公开(公告)日：2014-10-09

申请号：US14308339

申请日：2014-06-18

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Eric H. Freeman

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the plurality of conductive steps and insulated from at least another one of the conductive steps. Devices may include such conductive structures. Systems may include a semiconductor device and a stair step conductive structure having a plurality of contacts extending through a step of the stair step conductive structure. Methods of forming conductive structures include forming contacts in contact holes formed through at least one conductive step of a conductive structure. Methods of forming electrical connections in stair step conductive structures include forming contacts in contact holes formed through each step of the stair step conductive structure.

Abstract translation: 导电结构包括多个导电台阶和至少部分地穿过其延伸的接触件，与多个导电台阶中的至少一个连通，并与至少另一导电台阶绝缘。 设备可以包括这种导电结构。 系统可以包括半导体器件和楼梯级导电结构，其具有延伸穿过楼梯级导电结构的台阶的多个触点。 形成导电结构的方法包括在通过导电结构的至少一个导电步骤形成的接触孔中形成接触。 在楼梯级导电结构中形成电连接的方法包括在通过楼梯级导电结构的每个步骤形成的接触孔中形成触点。

公开(公告)号：US20130341798A1

公开(公告)日：2013-12-26

申请号：US14015696

申请日：2013-08-30

Applicant: Micron Technology, Inc.

Inventor： Eric H. Freeman ,  Michael A. Smith

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76892 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

公开(公告)号：US12112804B2

公开(公告)日：2024-10-08

申请号：US18237070

申请日：2023-08-23

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith ,  Martin W. Popp

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: G11C16/08 ,  G11C16/0483 ,  H01L29/1083 ,  H01L29/7833

Abstract: A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.

公开(公告)号：US20240274594A1

公开(公告)日：2024-08-15

申请号：US18426241

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Michael A. Smith

IPC: H01L27/02 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L27/0207 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/823864 ,  H01L25/0657 ,  H10B80/00 ,  H01L2225/06541

Abstract: A semiconductor device including a substrate; a plurality of active regions that are disposed on the substrate and that are parallelly aligned; a plurality of first type of trench isolations having a first top critical dimension (CD), each of the plurality of the first type of trench isolations including sidewalls that taper towards one another along a depth direction; and a plurality of second type of trench isolations having a second top CD, the second top CD being larger than the first top CD and each of the plurality of the second type of trench isolations having a flat bottom trench surface.