公开(公告)号：US20220270830A1

公开(公告)日：2022-08-25

申请号：US17179890

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma ,  Sidhartha Gupta

IPC: H01G11/26 ,  H01L27/105 ,  H01G11/08 ,  H01G11/36 ,  H01L49/02 ,  H01G11/86

Abstract: Some embodiments include an integrated assembly having a supercapacitor supported by a semiconductor substrate. The supercapacitor includes first and second electrode bases. The first electrode base includes first laterally-projecting regions, and the second electrode base includes second laterally-projecting regions which are interdigitated with the first laterally-projecting regions. A distance between the first and second laterally-projecting regions is less than or equal to about 500 nm. Carbon nanotubes extend upwardly from the first and second electrode bases. The carbon nanotubes are configured as a first membrane structure associated with the first electrode base and as a second membrane structure associated with the second electrode base. Pseudocapacitive material is dispersed throughout the first and second membrane structures. Electrolyte material is within and between the first and second membrane structures. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12079415B2

公开(公告)日：2024-09-03

申请号：US17963125

申请日：2022-10-10

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma

IPC: G06F3/041 ,  G06F3/01 ,  G06F3/0481 ,  G06F3/04817 ,  G06F3/0482 ,  G06F3/0484 ,  G06F3/04883 ,  G06F3/04886 ,  G06Q10/10 ,  G11B27/10 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H04L65/403 ,  H04N21/00 ,  H04N21/472 ,  H04N21/84 ,  H04N21/854

CPC classification number: G06F3/0416 ,  G06F3/0481 ,  G06F3/04817 ,  G06F3/0482 ,  G06F3/0484 ,  G06F3/04883 ,  G06F3/04886 ,  G06Q10/10 ,  H01L29/24 ,  H01L29/42324 ,  H01L29/7827 ,  H01L29/78391 ,  H01L29/7889 ,  H04L65/403 ,  H04N21/47205 ,  H04N21/854 ,  G06F3/01 ,  G06F2203/04105 ,  G06F2203/04803 ,  G06F2203/04808 ,  G11B27/10 ,  H04N21/00 ,  H04N21/84

Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230276624A1

公开(公告)日：2023-08-31

申请号：US17682514

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma ,  Naveen Kaushik ,  Sidhartha Gupta

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  G11C16/04 ,  H01L29/423 ,  H01L21/28 ,  H01L29/41 ,  H01L29/51

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  G11C16/0483 ,  H01L29/42344 ,  H01L29/40117 ,  H01L29/413 ,  H01L29/517

Abstract: An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures, and pillars vertically extending through the stack. The pillars comprise a tunnel dielectric material, a channel material, and an insulative material substantially surrounded by the channel material. The electronic device comprises a memory material horizontally adjacent to the conductive structures without being horizontally adjacent to the insulative structures. Related memory devices, systems, and methods of forming the electronic devices are also described.

公开(公告)号：US20230043781A1

公开(公告)日：2023-02-09

申请号：US17963125

申请日：2022-10-10

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma

IPC: G06F3/041 ,  G06F3/04883 ,  G06F3/0484 ,  H04L65/403 ,  G06F3/0481 ,  G06Q10/10 ,  G06F3/04886 ,  G06F3/04817 ,  G06F3/0482 ,  H04N21/472 ,  H04N21/854

Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11502179B2

公开(公告)日：2022-11-15

申请号：US17001660

申请日：2020-08-24

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma

IPC: H01L29/423 ,  H01L29/78 ,  H01L27/11597 ,  H01L27/1159 ,  H01L29/24 ,  H01L29/16

Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220238431A1

公开(公告)日：2022-07-28

申请号：US17161313

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Sidhartha Gupta ,  Pankaj Sharma ,  Haitao Liu

IPC: H01L23/522 ,  H01L27/11582 ,  G11C5/06 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/48

Abstract: A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and conductive structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the conductive structures. A sacrificial material is formed over the stack structure and pillar structures are formed to extend vertically through the stack structure and the sacrificial material. The method comprises forming conductive plug structures within upper portions of the pillar structures, forming slots extending vertically through the stack structure and the sacrificial material, at least partially removing the sacrificial material to form openings horizontally interposed between the conductive plug structures, and forming a low-K dielectric material within the openings. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20220059667A1

公开(公告)日：2022-02-24

申请号：US17001660

申请日：2020-08-24

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma

IPC: H01L29/423 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11597

Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210327881A1

公开(公告)日：2021-10-21

申请号：US16851588

申请日：2020-04-17

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Ke-Hung Chen ,  Christopher W. Petz ,  Pankaj Sharma ,  Yong Mo Yang

IPC: H01L27/108 ,  H01L49/02 ,  H01L27/07

Abstract: Some embodiments include an integrated assembly having capacitor-contact-regions. Metal-containing interconnects are coupled with the capacitor-contact-regions. A first insulative material is between the metal-containing interconnects. A second insulative material is over the first insulative material. A third insulative material is over the second insulative material. First capacitor electrodes extend through the second and third insulative materials and are coupled with the metal-containing interconnects. Fourth insulative material is adjacent the first capacitor electrodes. Capacitor plate electrodes are adjacent the fourth insulative material and are spaced from the first capacitor electrodes by the fourth insulative material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210265355A1

公开(公告)日：2021-08-26

申请号：US17317693

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma ,  Muralikrishnan Balakrishnan

IPC: H01L27/108 ,  H01L29/786 ,  H01L45/00 ,  H01L49/00 ,  G11C11/22 ,  H01L27/11502

Abstract: Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.

公开(公告)号：US11043497B1

公开(公告)日：2021-06-22

申请号：US16721006

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Pankaj Sharma ,  Muralikrishnan Balakrishnan

IPC: G11C13/00 ,  H01L27/108 ,  H01L45/00 ,  H01L49/00 ,  H01L29/786 ,  G11C11/22 ,  H01L27/11502 ,  G11C11/4091 ,  G11C11/408

Abstract: Some embodiments include a memory cell having a non-ohmic device between a transistor source/drain region and a capacitor. Some embodiments include a memory cell having a transistor with a first source/drain region, a second source/drain region, and a channel region between the first and second source/drain regions. A capacitor is electrically coupled to the second source/drain region through a non-ohmic device. The non-ohmic device includes a non-ohmic-device-material which changes conductivity in response to an electrical property along the channel region. The non-ohmic-device-material has a high-resistivity-mode when the electrical property along the channel region is below a threshold level, and transitions to a low-resistivity-mode when the electrical property along the channel region meets or exceeds the threshold level. Some embodiments include a memory array.