中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

37 records (took 0.015 seconds)

    METHODS OF OPERATING A MEMORY DEVICE
    11.
    发明申请
    METHODS OF OPERATING A MEMORY DEVICE 审中-公开

    公开(公告)号：US20180331110A1

    公开(公告)日：2018-11-15

    申请号：US16027598

    申请日：2018-07-05

    Applicant: Micron Technology, Inc.

    Inventor： Tieh-Chiang Wu

    IPC: H01L27/108 ,  H01L27/11582 ,  H01L49/02

    CPC classification number: H01L27/10823 ,  H01L27/10876 ,  H01L27/11582 ,  H01L28/00

    Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween.

    Semiconductor device comprising gate structure sidewalls having different angles
    15.
    发明授权
    Semiconductor device comprising gate structure sidewalls having different angles 有权

    公开(公告)号：US10468416B2

    公开(公告)日：2019-11-05

    申请号：US15700640

    申请日：2017-09-11

    Applicant: Micron Technology, Inc.

    Inventor： Tieh-Chiang Wu

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L27/108 ,  H01L21/308 ,  H01L21/336

    Abstract: The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.

    Semiconductor package with embedded MIM capacitor, and method of fabricating thereof
    16.
    发明授权
    Semiconductor package with embedded MIM capacitor, and method of fabricating thereof 有权

    公开(公告)号：US10381302B2

    公开(公告)日：2019-08-13

    申请号：US15396817

    申请日：2017-01-03

    Applicant: Micron Technology, Inc.

    Inventor： Shing-Yih Shih ,  Shih-Fan Kuan ,  Tieh-Chiang Wu

    IPC: H01L21/48 ,  H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065

    Abstract: An interposer includes a first redistribution layer, an organic substrate, a capacitor, a hard mask layer, a conductive pillar, and a second redistribution layer. The organic substrate is on the first redistribution layer. The capacitor is embedded in the organic substrate and includes a first electrode layer, a second electrode layer, and a capacitor dielectric layer between the first electrode layer and the second electrode layer. The first electrode layer electrically connects with the first redistribution layer. The hard mask layer is on the organic substrate. The conductive pillar is embedded in the organic substrate and the hard mask layer and electrically connects with the first redistribution layer. The second redistribution layer is on the hard mask layer and electrically connects with the second electrode layer and the conductive pillar.

    Methods of forming microelectronic structures having a patterned surface structure
    17.
    发明授权
    Methods of forming microelectronic structures having a patterned surface structure 有权

    公开(公告)号：US10354966B2

    公开(公告)日：2019-07-16

    申请号：US15966447

    申请日：2018-04-30

    Applicant: Micron Technology, Inc.

    Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

    IPC: H01L23/00

    Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

    Semiconductor devices comprising gate structure sidewalls having different angles
    19.
    发明授权
    Semiconductor devices comprising gate structure sidewalls having different angles 有权

    公开(公告)号：US09768175B2

    公开(公告)日：2017-09-19

    申请号：US14745464

    申请日：2015-06-21

    Applicant: Micron Technology, Inc.

    Inventor： Tieh-Chiang Wu

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L27/108 ,  H01L29/417

    CPC classification number: H01L27/10823 ,  H01L21/3085 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66659

    Abstract: The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.

    SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF
    20.
    发明申请
    SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF 审中-公开

    公开(公告)号：US20170213885A1

    公开(公告)日：2017-07-27

    申请号：US15003765

    申请日：2016-01-21

    Applicant: Micron Technology, Inc.

    Inventor： Tieh-Chiang Wu

    IPC: H01L49/02

    CPC classification number: H01L28/91

    Abstract: A semiconductor structure and a method of fabricating thereof are provided. The semiconductor structure includes a substrate and a capacitor structure. The substrate has a first blind hole and a trench. The first blind hole communicates with the trench. The first blind hole has a first depth, and the trench has a second depth smaller than the first depth. The capacitor structure includes a first inner conductor, a first inner insulator, and an outer conductor. The first inner conductor is in the first blind hole. The first inner insulator surrounds the first inner conductor. The outer conductor has a first portion surrounding the first inner insulator and an extending portion extending from the first portion. The first portion is in the first blind hole, and the extending portion is in the trench. The first inner conductor is separated from the outer conductor by the first inner insulator.

Patent Agency Ranking