中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

28 records (took 0.015 seconds)

    PILLAR-LAST METHODS FOR FORMING SEMICONDUCTOR DEVICES
    11.
    发明申请
    PILLAR-LAST METHODS FOR FORMING SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210166996A1

    公开(公告)日：2021-06-03

    申请号：US17175006

    申请日：2021-02-12

    Applicant: Micron Technology, Inc.

    Inventor： Anilkumar Chandolu ,  Wayne H. Huang ,  Sameer S. Vadhavkar

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

    Abstract: Semiconductor devices having one or more vias filled with an electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate having a first side, a plurality of circuit elements proximate to the first side, and a second side opposite the first side. A via can extend between the first and second sides, and a conductive material in the via can extend beyond the second side of the substrate to define a projecting portion of the conductive material. The semiconductor device can have a tall conductive pillar formed over the second side and surrounding the projecting portion of the conductive material, and a short conductive pad formed over the first side and electrically coupled to the conductive material in the via.

    Package cooling by coil cavity
    12.
    发明授权
    Package cooling by coil cavity 有权

    公开(公告)号：US10763186B2

    公开(公告)日：2020-09-01

    申请号：US16237111

    申请日：2018-12-31

    Applicant: Micron Technology, Inc.

    Inventor： Andrew M. Bayless ,  Wayne H. Huang ,  Owen R. Fay

    IPC: H01L23/31 ,  H01L23/473 ,  H01L21/56 ,  H01L23/36 ,  H01L23/467

    Abstract: A semiconductor device assembly can include a first die package comprising a bottom side; a top side; and lateral sides extending between the top and bottom sides. The assembly can include an encapsulant material encapsulating the first die package. In some embodiments, the assembly includes a cooling cavity in the encapsulant material. The cooling cavity can have a first opening; a second opening; and an elongate channel extending from the first opening to the second opening. In some embodiments, the elongate channel surrounds at least two of the lateral sides of the first die package. In some embodiments, the elongate channel is configured to accommodate a cooling fluid.

    METHODS AND SYSTEMS FOR MANUFACTURING PILLAR STRUCTURES ON SEMICONDUCTOR DEVICES
    13.
    发明申请
    METHODS AND SYSTEMS FOR MANUFACTURING PILLAR STRUCTURES ON SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200211993A1

    公开(公告)日：2020-07-02

    申请号：US16236237

    申请日：2018-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Yeruva ,  Owen R. Fay ,  Sameer S. Vadhavkar ,  Adriel Jebin Jacob Jebaraj ,  Wayne H. Huang

    IPC: H01L23/00

    Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

    Uniform back side exposure of through-silicon vias
    14.
    发明授权
    Uniform back side exposure of through-silicon vias 有权

    公开(公告)号：US10410879B2

    公开(公告)日：2019-09-10

    申请号：US15729391

    申请日：2017-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

    IPC: H01L21/321 ,  H01L21/768

    Abstract: Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.

    Uniform back side exposure of through-silicon vias
    15.
    发明授权
    Uniform back side exposure of through-silicon vias 有权

    公开(公告)号：US09818622B2

    公开(公告)日：2017-11-14

    申请号：US14608751

    申请日：2015-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

    IPC: H01L23/48 ,  H01L21/288 ,  H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/528

    CPC classification number: H01L21/3212 ,  H01L21/7684 ,  H01L21/76898

    Abstract: Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.

    METHODS AND SYSTEMS FOR MANUFACTURING PILLAR STRUCTURES ON SEMICONDUCTOR DEVICES
    16.
    发明申请
    METHODS AND SYSTEMS FOR MANUFACTURING PILLAR STRUCTURES ON SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210343670A1

    公开(公告)日：2021-11-04

    申请号：US17376934

    申请日：2021-07-15

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Yeruva ,  Owen R. Fay ,  Sameer S. Vadhavkar ,  Adriel Jebin Jacob Jebaraj ,  Wayne H. Huang

    IPC: H01L23/00

    Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

    PACKAGE COOLING BY COIL CAVITY
    17.
    发明申请
    PACKAGE COOLING BY COIL CAVITY 审中-公开

    公开(公告)号：US20200211916A1

    公开(公告)日：2020-07-02

    申请号：US16237111

    申请日：2018-12-31

    Applicant: Micron Technology, Inc.

    Inventor： Andrew M. Bayless ,  Wayne H. Huang ,  Owen R. Fay

    IPC: H01L23/31 ,  H01L23/473 ,  H01L23/467 ,  H01L23/36 ,  H01L21/56

    Abstract: A semiconductor device assembly can include a first die package comprising a bottom side; a top side; and lateral sides extending between the top and bottom sides. The assembly can include an encapsulant material encapsulating the first die package. In some embodiments, the assembly includes a cooling cavity in the encapsulant material. The cooling cavity can have a first opening; a second opening; and an elongate channel extending from the first opening to the second opening. In some embodiments, the elongate channel surrounds at least two of the lateral sides of the first die package. In some embodiments, the elongate channel is configured to accommodate a cooling fluid.

    UNIFORM BACK SIDE EXPOSURE OF THROUGH-SILICON VIAS
    20.
    发明申请
    UNIFORM BACK SIDE EXPOSURE OF THROUGH-SILICON VIAS 有权
    均匀的六面体六面体暴露

    公开(公告)号：US20160225695A1

    公开(公告)日：2016-08-04

    申请号：US14608751

    申请日：2015-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Jaspreet S. Gandhi ,  Wayne H. Huang

    IPC: H01L23/48 ,  H01L21/288 ,  H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/528

    CPC classification number: H01L21/3212 ,  H01L21/7684 ,  H01L21/76898

    Abstract: Systems and methods for uniform back side exposure of through-silicon vias (TSVs) are disclosed. In one embodiment, a semiconductor device comprises a substrate having a front side with circuit elements formed thereon, and a back side opposite the front side. A TSV extends between the front side and the back side of the substrate, and a dummy feature is disposed over the back side of the substrate, the dummy feature laterally spaced apart from the TSV and substantially coplanar with the TSV. In another embodiment, a semiconductor device comprises a substrate having a TSV formed therethrough, with a control material disposed over the back side of the substrate, the TSV substantially coplanar with the control material.

    Abstract translation: 公开了通过硅通孔（TSV）的均匀背侧曝光的系统和方法。 在一个实施例中，半导体器件包括具有形成在其上的电路元件的正面和与前侧相对的背面的衬底。 TSV在基板的正面和背面之间延伸，并且虚设特征设置在基板的背面上方，虚拟特征与TSV横向间隔开并与TSV基本上共面。 在另一个实施例中，半导体器件包括具有穿过其形成的TSV的衬底，其中控制材料设置在衬底的背面上，TSV与控制材料基本上共面。

Patent Agency Ranking