公开(公告)号：US06472926B2

公开(公告)日：2002-10-29

申请号：US09760639

申请日：2001-01-17

申请人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Mako Kobayashi ,  Mihoko Akiyama ,  Nobuyuki Fujii

发明人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Mako Kobayashi ,  Mihoko Akiyama ,  Nobuyuki Fujii

IPC分类号： G05F110

CPC分类号： G11C5/145 ,  G11C11/4074 ,  H02M3/073 ,  H02M2001/0032 ,  Y02B70/16

摘要： A plurality of pump modules are provided, the number of pump modules to be activated is changed depending on a mode of operation, and the number of pump modules to be activated is also adjusted with the specification of interest taken into consideration. There can be provided an internal voltage generation circuit occupying a small area and readily capable of accommodating a change in specification.

摘要翻译： 提供多个泵模块，根据操作模式改变待激活的泵模块的数量，并且还考虑要考虑的兴趣规格来调整要激活的泵模块的数量。 可以提供占用小面积并且容易适应规格变化的内部电压产生电路。

公开(公告)号：US06501326B2

公开(公告)日：2002-12-31

申请号：US09849392

申请日：2001-05-07

申请人： Nobuyuki Fujii ,  Fukashi Morishita ,  Akira Yamazaki ,  Yasuhiko Taito ,  Mako Okamoto

发明人： Nobuyuki Fujii ,  Fukashi Morishita ,  Akira Yamazaki ,  Yasuhiko Taito ,  Mako Okamoto

IPC分类号： G05F110

CPC分类号： H02M3/073 ,  G05F1/465

摘要： A capacitor (C12) is connected between a node (L) in a double boost part and the ground, and the amplitude of a repetitive pulse from the node (L) is made less than twice that of the power-supply voltage through utilization of charge and discharge of the capacitor (C12).

公开(公告)号：US06593642B2

公开(公告)日：2003-07-15

申请号：US09987257

申请日：2001-11-14

申请人： Mako Okamoto ,  Yasuhiko Taito ,  Fukashi Morishita ,  Akira Yamazaki ,  Nobuyuki Fujii

发明人： Mako Okamoto ,  Yasuhiko Taito ,  Fukashi Morishita ,  Akira Yamazaki ,  Nobuyuki Fujii

IPC分类号： G01F110

CPC分类号： H01L27/10897 ,  G11C11/4074 ,  H01L27/0218

摘要： A DRAM is provided at a portion relating to generation of a boosted potential with a filter circuit located between a detector circuit and a ring oscillator for removing a pulse-like change in level from an output signal of the detector circuit. Accordingly, temporary stop of the charge pump circuit can be prevented even when the boosted potential exceeds in a pulse-like manner the reference potential at the vicinity of the output node of the charge pump circuit, and the boosted potential can be rapidly restored to the reference potential.

摘要翻译： 在与产生升压电位有关的部分中提供DRAM，该滤波电路位于检测器电路和环形振荡器之间，用于从检测器电路的输出信号中去除脉冲状的电平变化。 因此，即使当升压电位以类似脉冲的方式超过电荷泵电路的输出节点附近的基准电位时，也可以防止电荷泵电路的暂时停止，并且可以将升压电位迅速恢复到 参考潜力。

公开(公告)号：US07030681B2

公开(公告)日：2006-04-18

申请号：US10118432

申请日：2002-04-09

申请人： Akira Yamazaki ,  Fukashi Morishita ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mako Okamoto

发明人： Akira Yamazaki ,  Fukashi Morishita ,  Yasuhiko Taito ,  Nobuyuki Fujii ,  Mako Okamoto

IPC分类号： G05F1/10

CPC分类号： G11C5/146

摘要： Well bias voltages are generated in accordance with a logic power supply voltage and a memory power supply voltage. The transistor included in a control circuit in a memory core is constituted of a logic transistor manufactured through the same manufacturing steps as those for the transistors of a logic formed on the same semiconductor substrate. Well bias voltages (VBB, VPP) are applied to a back gate of this logic transistor. A memory integrated with a logic on a common semiconductor substrate is provided which allows a transistor of a control circuit therein to be manufactured through the same manufacturing process as that of the logic and allows reduction of current consumption.

公开(公告)号：US06665217B2

公开(公告)日：2003-12-16

申请号：US10120575

申请日：2002-04-12

申请人： Fukashi Morishita ,  Yasuhiko Taito ,  Akira Yamazaki ,  Mako Okamoto ,  Nobuyuki Fujii

发明人： Fukashi Morishita ,  Yasuhiko Taito ,  Akira Yamazaki ,  Mako Okamoto ,  Nobuyuki Fujii

IPC分类号： G11C700

CPC分类号： G11C5/025 ,  G11C5/147

摘要： A tuning control circuit includes fuse devices each shifting from a conductive state to an interrupted state in response to a program input from the outside, and signal driving circuits for driving the signal levels of tuning control signals in accordance with the states of the fuse devices. A reference voltage generating circuit generates a reference voltage corresponding to a reference value of a memory array voltage of a semiconductor memory device according to the invention in accordance with an electrical resistance value which is finely adjusted in response to the tuning control signals.

摘要翻译： 调谐控制电路包括响应于来自外部的程序输入而从导通状态转换到中断状态的熔丝器件，以及根据保险丝器件的状态来驱动调谐控制信号的信号电平的信号驱动电路。 参考电压产生电路根据根据本发明的半导体存储器件的存储器阵列电压的参考值产生与根据调谐控制信号精细调节的电阻值相对应的参考电压。

公开(公告)号：US06373763B1

公开(公告)日：2002-04-16

申请号：US09839403

申请日：2001-04-23

申请人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mako Okamoto

发明人： Yasuhiko Taito ,  Akira Yamazaki ,  Fukashi Morishita ,  Nobuyuki Fujii ,  Mako Okamoto

IPC分类号： G11C700

CPC分类号： G11C7/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094

摘要： An equalizing circuit includes a plurality of N-channel MOS transistors for respectively setting a data line to a predetermined precharge voltage. The H-level voltage Vddb of a control signal for turning on these N-channel MOS transistors is set to a range higher than the sum of the precharge voltage and a transistor threshold voltage. A Vddb generation circuit steps up an external power-supply voltage and sets a voltage Vddb in a range lower than a step-up voltage for activating a word line.

摘要翻译： 均衡电路包括用于分别将数据线设置为预定预充电电压的多个N沟道MOS晶体管。 用于接通这些N沟道MOS晶体管的控制信号的H电平电压Vddb被设置为高于预充电电压和晶体管阈值电压之和的范围。 Vddb生成电路升高外部电源电压，并将电压Vddb设置在低于用于激活字线的升压电压的范围内。

公开(公告)号：US08258604B2

公开(公告)日：2012-09-04

申请号：US12647445

申请日：2009-12-26

申请人： Koji Bando ,  Kazuyuki Misumi ,  Tatsuhiko Akiyama ,  Naoki Izumi ,  Akira Yamazaki

发明人： Koji Bando ,  Kazuyuki Misumi ,  Tatsuhiko Akiyama ,  Naoki Izumi ,  Akira Yamazaki

IPC分类号： H01L23/552

CPC分类号： H01L23/49503 ,  G11C11/16 ,  H01L23/552 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L27/228 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01061 ,  H01L2924/01064 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2924/00012

摘要： To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device.A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.

摘要翻译： 提供一种通过提高包括MRAM器件的半导体器件中的外部磁场的电阻来提高MRAM器件的数据保持特性的技术。 第一磁屏蔽材料经由第一管芯附着膜设置在管芯焊盘上。 然后，半导体芯片通过第二芯片附着膜安装在第一磁屏蔽材料上。 此外，第二磁屏蔽材料通过第三芯片附着膜设置在半导体芯片的上方。 也就是说，半导体芯片被布置成被第一磁屏蔽材料和第二磁屏蔽材料夹在中间。 此时，当第二磁屏蔽材料的平面区域小于第一磁屏蔽材料的平面区域时，第二磁屏蔽材料的厚度比第一磁屏蔽材料的厚度厚。

公开(公告)号：US20070170573A1

公开(公告)日：2007-07-26

申请号：US11617239

申请日：2006-12-28

申请人： Soshi KURODA ,  Naoya Yasuda ,  Hideyuki Arakawa ,  Akira Yamazaki ,  Koji Bando

发明人： Soshi KURODA ,  Naoya Yasuda ,  Hideyuki Arakawa ,  Akira Yamazaki ,  Koji Bando

IPC分类号： H01L23/02

CPC分类号： H01L23/5386 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/544 ,  H01L23/552 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/6611 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/13144 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48478 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/85001 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/20753 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/20752 ,  H01L2224/4554

摘要： The semiconductor device with which bonding wires cannot contact easily is offered.In this semiconductor device, memory chips are stacked on the surface of a wiring substrate, a microcomputer chip and an interposer chip are arranged on the surface of the memory chip, and the pad of a microcomputer chip and the pad of an interposer chip arranged almost circularly are connected by a bonding wire. Therefore, since the transfer pressure of liquid resin for sealing can be weakened with a wire, contact of the wires by deformation of a wire can be prevented.

摘要翻译： 提供接合线不容易接触的半导体器件。 在该半导体装置中，将存储芯片层叠在布线基板的表面上，在存储芯片的表面配置有微型计算机芯片和插入式芯片，微型计算机芯片的焊盘和插入器芯片的焊盘几乎布置 圆形通过接合线连接。 因此，由于可以用线弱化用于密封的液态树脂的转印压力，因此可以防止由于电线的变形引起的电线的接触。

公开(公告)号：US07009781B2

公开(公告)日：2006-03-07

申请号：US10873347

申请日：2004-06-22

申请人： Atsushi Oshima ,  Akira Yamazaki ,  Yasutaka Koga

发明人： Atsushi Oshima ,  Akira Yamazaki ,  Yasutaka Koga

IPC分类号： G02B15/14

CPC分类号： G02B7/102

摘要： A zoom lens mechanism foldable and retractable to be used in a digital still camera to control zooming of the zoom lens uses programmed data written in a micro controller unit (hereinafter referred to as MCU) instead of the conventional cylindrical grooved cams that are usually used to mechanically control zooming of a zoom lens of a digital still camera, and the assembly of the second lens group is rotatable inside the lens barrel, and the first lens group can be folded and retracted into the space provided by the rotation of the second lens assembly.

摘要翻译： 可变形和可缩回以用于数字静态照相机以控制变焦镜头变焦的变焦透镜机构使用写在微控制器单元（以下称为MCU）中的编程数据代替常规的圆柱形凹槽凸轮，通常用于 机械地控制数字静态照相机的变焦镜头的变焦，并且第二透镜组的组合可在透镜镜筒内旋转，并且第一透镜组可被折叠并缩回到由第二透镜组件的旋转所提供的空间 。

公开(公告)号：US06995468B2

公开(公告)日：2006-02-07

申请号：US10798345

申请日：2004-03-12

申请人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

发明人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

IPC分类号： H01L23/34 ,  H01L21/48

CPC分类号： H01L24/83 ,  H01L21/2007 ,  H01L23/49513 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2924/01004 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/07802

摘要： In a semiconductor device fabricating method, a plurality of wafers each having a plurality of chips into is carried and is placed in a die bonder. Chips taken out from the plurality of wafers is bonded together, respectively, and superpose in a stack by bonding layers to form a chip assembly. The chip assembly to a die pad by a bonding layer is bonded. Thus, the die bonder is able to bond the chip assembly consisting of the plurality of chips to the die pad, so that the process time of a die bonding process for bonding the plurality of chips to the die pad is comparatively short, the semiconductor fabricating apparatus produces semiconductor devices at an improved productivity, has a comparatively small scale and needs a comparatively low equipment investment.

摘要翻译： 在半导体器件制造方法中，将具有多个芯片的多个晶片承载并放置在管芯接合器中。 从多个晶片取出的芯片分别结合在一起，并通过结合层叠在堆叠中以形成芯片组件。 通过接合层将芯片组合到芯片焊盘。 因此，芯片接合器能够将由多个芯片组成的芯片组件接合到芯片焊盘，使得用于将多个芯片接合到管芯焊盘的管芯接合工艺的处理时间相对较短，半导体制造 设备以提高生产率生产半导体器件，规模相对较小，需要相对较低的设备投资。