公开(公告)号：US20220114069A1

公开(公告)日：2022-04-14

申请号：US17556473

申请日：2021-12-20

Applicant: NVIDIA Corporation

Inventor： Jonah ALBEN ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

IPC: G06F11/267 ,  G06F11/22 ,  G06F1/3296 ,  G06F11/273 ,  G06F11/27

Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

公开(公告)号：US20210286693A1

公开(公告)日：2021-09-16

申请号：US16818327

申请日：2020-03-13

Applicant: NVIDIA Corporation

Inventor： Jonah ALBEN ,  Sachin Idgunji ,  Jue Wu ,  Shantanu Sarangi

IPC: G06F11/267 ,  G06F11/22 ,  G06F11/27 ,  G06F11/273 ,  G06F1/3296

Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.

公开(公告)号：US10545189B2

公开(公告)日：2020-01-28

申请号：US15336716

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Milind Sonawane ,  Amit Sanghani ,  Jonathon E. Colburn ,  Bala Tarun Nelapatla ,  Shantanu Sarangi ,  Rajendra Kumar reddy.S ,  Sailendra Chadalavada

IPC: G01R31/3177 ,  G01R31/26 ,  G01R31/3185 ,  G06F11/00 ,  G01R31/317 ,  G01R31/28

Abstract: In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.

公开(公告)号：US20170115338A1

公开(公告)日：2017-04-27

申请号：US15336687

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Sailendra Chadalavda ,  Shantanu Sarangi ,  Milind Sonawane ,  Amit Sanghani ,  Jonathon E. Colburn ,  Dan Smith ,  Jue Wu ,  Mahmut Yilmaz

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/2607 ,  G01R31/2803 ,  G01R31/2806 ,  G01R31/2834 ,  G01R31/31701 ,  G01R31/31707 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318555 ,  G01R31/318572 ,  G06F11/00

Abstract: In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.

公开(公告)号：US20240132083A1

公开(公告)日：2024-04-25

申请号：US18048952

申请日：2022-10-23

Applicant: NVIDIA Corporation

Inventor： Anitha Kalva ,  Jae Wu ,  Shantanu Sarangi ,  Sailendra Chadalavada ,  Milind Sonawane ,  Chen Fang ,  Abilash Nerallapally

IPC: B60W50/02

CPC classification number: B60W50/0205 ,  B60W2050/0044

Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.

公开(公告)号：US11867744B2

公开(公告)日：2024-01-09

申请号：US17075629

申请日：2020-10-20

Applicant: NVIDIA CORPORATION

Inventor： Animesh Khare ,  Ashish Kumar ,  Shantanu Sarangi ,  Rahul Garg ,  Sailendra Chadalavada

IPC: G01R31/26 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F13/42

CPC classification number: G01R31/2601 ,  G01R31/2639 ,  G01R31/31725 ,  G01R31/318328 ,  G01R31/318536 ,  G06F13/4221 ,  G06F2213/0026

Abstract: Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.

公开(公告)号：US20230146920A1

公开(公告)日：2023-05-11

申请号：US17979246

申请日：2022-11-02

Applicant: NVIDIA CORPORATION

Inventor： Bonita Bhaskaran ,  Nithin Valentine ,  Shantanu Sarangi ,  Mahmut Yilmaz ,  Suhas Satheesh ,  Charlie Hwang ,  Tezaswi Raja ,  Kevin Zhou ,  Sailendra Chadalavada ,  Kevin Ye ,  Seyed Nima Mozaffari Mojaveri ,  Kerwin Fu

IPC: G01R31/317 ,  G01R29/26 ,  G01R31/3177

CPC classification number: G01R31/31708 ,  G01R31/31727 ,  G01R29/26 ,  G01R31/31725 ,  G01R31/3177 ,  G01R31/31905

Abstract: Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.

公开(公告)号：US20220382659A1

公开(公告)日：2022-12-01

申请号：US17883199

申请日：2022-08-08

Applicant: NVIDIA Corporation

Inventor： Shantanu Sarangi ,  Jae Wu ,  Andi Skende ,  Rajith Mavila

IPC: G06F11/27 ,  G06F11/267 ,  G06F11/22

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

公开(公告)号：US20220365857A1

公开(公告)日：2022-11-17

申请号：US17320025

申请日：2021-05-13

Applicant: NVIDIA Corporation

Inventor： Sailendra Chadalavada ,  Anitha Kalva ,  Abilash Nerallapally ,  Milind Sonawane ,  Shantanu Sarangi ,  Ashok Aravamudhan ,  Sridharan Ramakrishnan ,  Sam Edirisooriya ,  Hari Krishnan

IPC: G06F11/263 ,  G06F11/27 ,  G06F11/273 ,  G06F11/14

Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.

公开(公告)号：US10444280B2

公开(公告)日：2019-10-15

申请号：US15336676

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Dheepakkumaran Jayaraman ,  Karthikeyan Natarajan ,  Shantanu Sarangi ,  Amit Sanghani ,  Milind Sonawane ,  Sailendra Chadalavda ,  Jonathon E. Colburn ,  Kevin Wilder ,  Mahmut Yilmaz ,  Pavan Kumar Datla Jagannadha

IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/26 ,  G06F11/00 ,  G01R31/317 ,  G01R31/28

Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.