利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

25 条记录 (耗时 0.05 秒)

    Aluminum-germanium alloys for VLSI metallization
    11.
    发明授权
    Aluminum-germanium alloys for VLSI metallization 失效
    用于VLSI金属化的铝 - 锗合金

    公开(公告)号：US5308794A

    公开(公告)日：1994-05-03

    申请号：US108781

    申请日：1993-08-18

    申请人： King-Ning Tu

    发明人： King-Ning Tu

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/532 ,  H01L21/44

    CPC分类号： H01L21/76877 ,  H01L23/53219 ,  H01L2924/0002

    摘要： An apparatus and method for forming an interconnect through an opening or on an insulation layer with the coefficient of thermal expansion of the interconnect adjusted to reduce the thermal stress between the interconnect and the insulation layer is described incorporating the steps of forming a solid solution of a binary alloy including germanium and aluminum or a ternary alloy including aluminum, germanium and a third element, for example silicon, and forming a precipitate from the solid solution at a reduced temperature with respect to the temperature of forming the solid solution whereby the volume of the precipitate including germanium and the remaining solid solution is larger than the volume of the original solid solution.

    摘要翻译： 描述了一种用于通过开口或绝缘层形成互连件的装置和方法，其中调节互连件的热膨胀系数以减小互连件和绝缘层之间的热应力，其包括以下步骤：形成 包括锗和铝的二元合金或包括铝，锗和第三元素例如硅的三元合金，并且在相对于形成固溶体的温度的降低的温度下从固溶体形成沉淀物，由此， 包括锗和剩余的固溶体的沉淀物大于原始固溶体的体积。

    Electrical multilayer contact for microelectronic structure
    12.
    发明授权
    Electrical multilayer contact for microelectronic structure 失效
    微电子结构的电气多层接触

    公开(公告)号：US4980751A

    公开(公告)日：1990-12-25

    申请号：US383224

    申请日：1989-07-19

    申请人： Moshe Eizenberg ,  King-Ning Tu

    发明人： Moshe Eizenberg ,  King-Ning Tu

    IPC分类号： H01L23/532 ,  H01L29/45

    CPC分类号： H01L29/456 ,  H01L23/53223 ,  H01L24/05 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/14

    摘要： An electrical contact between two film members that is stable over all conditions encountered in processing and over the device lifetime. The contact has a central multi-element diffusion barrier alloy layer having at least one elemental ingredient that does not react with either film member and at least one other elemental ingredient that reacts with the adjacent film member to form an intermediate layer between the diffusion barrier layer and each film member. A contact between aluminum wiring and silicon devices on an integrated circuit chip is provided with a diffusion barrier layer of for example, WPd with an intermediate layer on both sides, one side being PdSi next to the silicon and the other being AlPd.sub.3 next to the aluminum.

    摘要翻译： 两个膜构件之间的电接触在处理中遇到的所有条件下以及器件寿命都是稳定的。 接触件具有中心多元件扩散阻挡合金层，其具有至少一种元素成分，其不与膜构件和至少一种其它元素成分反应，所述至少一种元素成分与相邻的膜构件反应以在扩散阻挡层 和每个电影成员。 在集成电路芯片上的铝布线和硅器件之间的接触件设置有例如WPd的扩散阻挡层，WPd的两侧具有中间层，一侧为硅的旁边的PdSi，而另一侧为与铝相邻的AlPd3 。

    METHODS OF FABRICATING HIGHLY CONDUCTIVE REGIONS IN SEMICONDUCTOR SUBSTRATES FOR RADIO FREQUENCY APPLICATIONS
    13.
    发明申请
    METHODS OF FABRICATING HIGHLY CONDUCTIVE REGIONS IN SEMICONDUCTOR SUBSTRATES FOR RADIO FREQUENCY APPLICATIONS 有权
    在无线电频率应用的半导体基板中制造高导电区域的方法

    公开(公告)号：US20070117345A1

    公开(公告)日：2007-05-24

    申请号：US11626255

    申请日：2007-01-23

    申请人： King-Ning Tu ,  Ya-Hong Xie ,  Chang-Ching Yeh

    发明人： King-Ning Tu ,  Ya-Hong Xie ,  Chang-Ching Yeh

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.

    摘要翻译： 用于在射频应用的半导体衬底中制造高导电区域的方法用于制造两种结构：（1）第一结构包括遍及Si衬底的整个厚度的多孔硅（硅）区域，其允许随后形成金属化柱 和多孔区域中的金属化护城河; 和（2）第二结构包括从衬底的前部和/或背面蚀刻到Si衬底或某些其它半导体衬底中的交错的深V形槽或沟槽，其中这些V形槽和沟槽被填充或涂覆 用金属形成金属化的护城河。

    Method for making planar 3D heterepitaxial semiconductor structures with buried epitaxial silicides
    15.
    发明授权
    Method for making planar 3D heterepitaxial semiconductor structures with buried epitaxial silicides 失效
    制造具有埋入式外延硅化物的平面三维等离子体半导体结构的方法

    公开(公告)号：US4728626A

    公开(公告)日：1988-03-01

    申请号：US799043

    申请日：1985-11-18

    申请人： King-Ning Tu

    发明人： King-Ning Tu

    IPC分类号： H01L21/20 ,  H01L21/74 ,  H01L27/00 ,  H01L29/41 ,  H01L29/48 ,  H01L23/54

    CPC分类号： H01L21/74 ,  H01L21/02381 ,  H01L21/02425 ,  H01L21/02428 ,  H01L21/02532 ,  H01L21/02658 ,  H01L2924/0002

    摘要： A 3D epitaxial structure is described in which metal compounds are formed in a semiconductor layer, the metal compounds being epitaxial with the semiconductor layer and having a top surface which is planar with the top surface of the semiconductor layer. Onto this another layer can be epitaxially grown, such as an additional semiconductor layer. The technique for forming such a structure utilizes a starting material for metal compound formation which leaves a residue that is preferentially etched in order to preserve the embedded metal compound and to leave a substantially planar surface comprising the metal compound epitaxial regions and the unreacted surface regions of the semiconductor layer.

    摘要翻译： 描述了一种三维外延结构，其中在半导体层中形成金属化合物，金属化合物与半导体层外延，并具有与半导体层的顶表面平面的顶表面。 可以外延生长该另一层，例如附加的半导体层。 用于形成这种结构的技术利用金属化合物形成的起始材料，其留下优先蚀刻的残余物，以便保留嵌入的金属化合物并留下基本平坦的表面，其包含金属化合物外延区域和未反应的表面区域 半导体层。

    Method for improving dielectric breakdown strength of insulating-glassy-material layer of a device including ion implantation therein
    16.
    发明授权
    Method for improving dielectric breakdown strength of insulating-glassy-material layer of a device including ion implantation therein 失效
    用于改善包括其中植入物的装置的绝缘玻璃材料层的介电断裂强度的方法

    公开(公告)号：US4001049A

    公开(公告)日：1977-01-04

    申请号：US585924

    申请日：1975-06-11

    申请人： John E. Baglin ,  Thomas H. DiStefano ,  King-Ning Tu

    发明人： John E. Baglin ,  Thomas H. DiStefano ,  King-Ning Tu

    IPC分类号： H01L21/265 ,  C03C23/00 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/316 ,  H01L29/51

    CPC分类号： H01L21/28185 ,  C03C23/0055 ,  H01L21/31155 ,  H01L29/51 ,  Y10S438/91

    摘要： It has been discovered for the practice of this disclosure that a particular ion radiation treatment of amorphous SiO.sub.2 thin film, with a subsequent annealing procedure, improves the dielectric breakdown property of the film. The treated SiO.sub.2 film is found to be substantially more dense than a comparable untreated SiO.sub.2 film. It is theorized for the practice of this disclosure that the physical mechanism which produces the densification of the SiO.sub.2 film may be responsible for the enhanced dielectric properties of the film. Such an improved film is especially useful as the gate insulator layer in an insulated-gate electrode field-effect transistor device, and as an insulating layer for electrically separating two metallic films in a thin film integrated circuit. Such SiO.sub.2 thin films are useful in integrated circuit technology because the electrical insulation property thereof is considerably improved, e.g., in metal-oxide-semiconductor field effect devices in which the gate insulation is relatively thin, e.g. less than 500A, and in metallic magnetic-bubble devices in which a thin SiO.sub.2 layer is used to separate the sense element from the conductive magnetic film.

    Specimen box for electron microscope
    18.
    发明授权
    Specimen box for electron microscope 有权
    电子显微镜样品盒

    公开(公告)号：US08405047B2

    公开(公告)日：2013-03-26

    申请号：US13450271

    申请日：2012-04-18

    申请人： Chih Chen ,  King-Ning Tu

    发明人： Chih Chen ,  King-Ning Tu

    IPC分类号： G21K5/08

    CPC分类号： H01J37/20 ,  H01J2237/2003

    摘要： The present invention relates to a specimen box for an electron microscope, comprising a first substrate, a second substrate, one or more photoelectric elements, and a metal adhesion layer. The first substrate has a first surface, a second surface, a first concave, and one or more first through holes, wherein the first through holes penetrate through the first substrate. The second substrate has a third surface, a forth surface, and a second concave. The photoelectric element is disposed between the first substrate and the second substrate. In addition, the metal adhesion layer is disposed between the first substrate and the second substrate to form a space for a specimen contained therein. Besides, the present specimen box further comprises one or more plugs. When the plugs are assembled into the first through holes to seal the specimen box, the in-situ observation can be accomplished by using the electron microscope.

    摘要翻译： 本发明涉及一种用于电子显微镜的标本盒，包括第一基底，第二基底，一个或多个光电元件和金属粘合层。 第一基板具有第一表面，第二表面，第一凹部和一个或多个第一通孔，其中第一通孔穿过第一基板。 第二基板具有第三表面，第四表面和第二凹部。 光电元件设置在第一基板和第二基板之间。 此外，金属粘合层设置在第一基板和第二基板之间，以形成其中容纳的样本的空间。 此外，本标本箱还包括一个或多个插头。 当插头组装到第一通孔中以密封标本盒时，可以通过使用电子显微镜来实现原位观察。