Abstract:
One embodiment of the present invention provides systems and techniques for generating a transistor-level description of a subcircuit. A user may want to simulate a subcircuit in a circuit using a transistor-level simulator, and one or more cells in the subcircuit may need to be sensitized so that the cells are in a desired state when the subcircuit is simulated. An embodiment modifies the subcircuit by inserting analog switches in front of the cells that need to be sensitized, so that the analog switches can be used to apply a sensitization sequence to the cells during the transistor-level simulation. The embodiment can then generate a transistor-level description of the modified subcircuit. Next, the transistor-level description of the subcircuit can be stored, thereby enabling the transistor-level simulator to simulate the subcircuit.
Abstract:
The invention “Ion Trap Array (ITA)” pertains generally to the field of ion storage and analysis technologies, and particularly to the ion storing apparatus and mass spectrometry instruments which separate ions by its character such as mass-to-charge ratio. The aim of this invention is providing an apparatus for ion storage and analysis comprising at least two or more rows of parallel placed electrode array wherein each electrode array includes at least two or more parallel bar-shaped electrodes, by applying different phase of alternating current voltages on different bar electrodes to create alternating electric fields inside the space between two parallel electrodes of different rows of electrode arrays, multiple linear ion trapping fields paralleled constructed in the space between the different rows of electrode arrays which are open to adjacent each other without a real barrier. This invention also provides a method for ion storage and analysis involving with the trapping, cooling and mass-selected analyzing of ions by this apparatus mentioned which constructs multiple conjoint linear ion trapping fields in the space between the different rows of electrode arrays
Abstract:
A method for modifying the refractive index of an optical, hydrogel polymeric material. The method comprises irradiating predetermined regions of an optical, polymeric material with a laser to form refractive structures. To facilitate the formation of the refractive structures the optical, hydrogel polymeric material comprises a photosensitizer. The presence of the photosensitizer permits one to set a scan rate to a value that is at least fifty times greater than a scan rate without the photosensitizer in the material, yet provides similar refractive structures in terms of the observed change in refractive index. Alternatively, the photosensitizer in the polymeric material permits one to set an average laser power to a value that is at least two times less than an average laser power without the photosensitizer in the material, yet provide similar refractive structures.
Abstract:
The invention provides human secreted proteins (SECP) and polynucleotides which identify and encode SECP. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with aberrant expression of SECP.
Abstract:
A method to perform timing analysis for a complex logic cell with distorted input waveform and coupled load networks is presented. Timing arc based models are used in conjunction with CCB based current models of portions of the logic cell to compute the output signal of the logic cell. For example, an intermediary signal is generated using a first timing arc based model and an equivalent coupled network output signal is generated using a channel connected block (CCB) based current model.
Abstract:
A system and method for testing a Link Control Card (LCC) of a storage device includes a host, a middle plane (MP), a switch, and a testing device array. The host is connected to the testing device array for sending out command sets and receiving results. The MP is connected between the LCC and the testing device array. The switch determines the LCC to output hard reset signals and the hard reset signals are transferred to the testing device array via the MP. The testing device array includes a plurality of testing devices, and each of the testing devices includes a micro-controller unit (MCU); a connector being connected to the MCU, and coupled to the MP; an address setting unit being connected to the MCU, for setting an unique address of each of the testing devices; and a first interface being connected to the MCU for outputting results.
Abstract:
The invention provides human G-protein coupled receptors (GCREC) and polynucleotides which identify and encode GCREC. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with aberrant expression of GCREC.
Abstract:
The invention provides human phosphodiesterases (HPDE) and polynucleotides which identify and encode HPDE. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with aberrant expression of HPDE.
Abstract:
The invention provides human adenylyl and guanylyl cyclases (ADGUC) and polynucleotides which identify and encode ADGUC. The invention also provides expression vectors, host cells, antibodies, agonists, and antagonists. The invention also provides methods for diagnosing, treating, or preventing disorders associated with aberrant expression of ADGUC.
Abstract:
A method of fast start and/or fast termination of a radio frequency resonator, which has a coil, a capacitor and two switches with internal resistance wherein one end of the switches is connected to a junction of the coil and the capacitor where a RF voltage is provided, and another end of each switch is connected to high voltage power supplies with opposite polarities, a fast start being achieved by closing one of the switches for a short period of time for fast start, and a fast termination being obtained by closing both switches for a while.