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    PARTIAL RESPONSE DECISION FEEDBACK EQUALIZER WITH SELECTION CIRCUITRY HAVING HOLD STATE
    11.
    发明申请
    PARTIAL RESPONSE DECISION FEEDBACK EQUALIZER WITH SELECTION CIRCUITRY HAVING HOLD STATE 有权

    公开(公告)号：US20130342240A1

    公开(公告)日：2013-12-26

    申请号：US13915290

    申请日：2013-06-11

    Applicant: Rambus Inc.

    Inventor： Amir Amirkhany ,  Kambiz Kaviani ,  Aliazam Abbasfar

    IPC: H03K5/24

    CPC classification number: H04L25/03949 ,  H03K5/24

    Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

    Folded memory modules
    14.
    发明授权
    Folded memory modules 有权

    公开(公告)号：US10380053B2

    公开(公告)日：2019-08-13

    申请号：US15289785

    申请日：2016-10-10

    Applicant: Rambus Inc.

    Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

    IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

    Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

    Modulated on-die termination
    17.
    发明授权
    Modulated on-die termination 有权
    调制片上端接

    公开(公告)号：US09281816B2

    公开(公告)日：2016-03-08

    申请号：US14368772

    申请日：2012-12-22

    Applicant: Rambus Inc.

    Inventor： Amir Amirkhany ,  Farshid Aryanfar ,  Ravindranath Kollipara ,  Xingchao (Chuck) Yuan

    IPC: H03K19/00 ,  H03K19/0175 ,  H04L25/02 ,  G11C29/50 ,  G06F13/40

    CPC classification number: H03K19/0005 ,  G06F13/4086 ,  G11C29/50008 ,  H03K19/017545 ,  H04L25/0278

    Abstract: Alternating on-die termination impedances are applied within an integrated circuit device to up-convert signal reflections to higher frequencies that are attenuated by the signaling channel as the reflections propagate toward an intended signal receiver. Through this approach, the disruptive effect of reflected signals may be significantly reduced with relatively little overhead within the interconnected integrated circuit devices and little or no change to the printed circuit board or other interconnect medium. Changes to the printed circuit board or other interconnect medium can be made to further increase attenuation over the frequency band of the up-converted reflection and outside of the transmission band of signals of interest.

    Abstract translation: 在集成电路器件内施加交替的片上终端阻抗，以将信号反射上变频到由信号通道衰减的较高频率，因为反射向预期信号接收器传播。 通过这种方法，相互连接的集成电路器件内的相对较少的开销可以显着降低反射信号的破坏性影响，并且对印刷电路板或其它互连介质几乎没有或没有改变。 可以对印刷电路板或其它互连介质进行改变，以进一步增加在上变频反射的频带和感兴趣的信号的传输频带之外的衰减。

    DATA BUFFER WITH A STROBE-BASED PRIMARY INTERFACE AND A STROBE-LESS SECONDARY INTERFACE
    18.
    发明申请
    DATA BUFFER WITH A STROBE-BASED PRIMARY INTERFACE AND A STROBE-LESS SECONDARY INTERFACE 有权
    数据缓冲器与基于STROBE的主界面和无障碍二次接口

    公开(公告)号：US20140101382A1

    公开(公告)日：2014-04-10

    申请号：US14028172

    申请日：2013-09-16

    Applicant: RAMBUS INC.

    Inventor： Kambiz Kaviani ,  Amir Amirkhany ,  Dinesh Patil ,  Mohammad Hekmat

    IPC: G06F12/02

    CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0683 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/20 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/1093

    Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

    Abstract translation: 描述了具有基于选通脉冲的主界面和在存储器模块上使用的无频闪次要接口的数据缓冲器。 一个存储器模块包括地址缓冲器，数据缓冲器和多个动态随机存取存储器（DRAM）器件。 地址缓冲器通过无闪光次要接口向数据缓冲器和DRAM器件提供定时参考，用于数据缓冲器和DRAM器件之间的一个或多个事务。

    OPTIMIZING POWER IN A MEMORY DEVICE
    20.
    发明申请
    OPTIMIZING POWER IN A MEMORY DEVICE 有权

    公开(公告)号：US20220350390A1

    公开(公告)日：2022-11-03

    申请号：US17748704

    申请日：2022-05-19

    Applicant: Rambus Inc.

    Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

    IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06

    Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

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