公开(公告)号：US11836099B2

公开(公告)日：2023-12-05

申请号：US17548510

申请日：2021-12-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright ,  John Eric Linstadt ,  Craig Hampel

IPC: G06F13/16 ,  G06F12/0868 ,  G06F12/0888 ,  G11C7/10 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0895 ,  G06F13/28 ,  G11C29/52

CPC classification number: G06F13/1678 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1068 ,  G06F12/0868 ,  G06F12/0888 ,  G06F12/0895 ,  G06F13/28 ,  G11C7/10 ,  G11C29/52 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/403

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.

公开(公告)号：US11836044B2

公开(公告)日：2023-12-05

申请号：US18070732

申请日：2022-11-29

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/1076

Abstract: A programmable crossbar matrix or an array of steering multiplexors (MUXs) coalesces (i.e., routes) the data values from multiple known “bad” bit positions within multiple symbols of a codeword, to bit positions within a single codeword symbol. The single codeword symbol receiving the known “bad” bit positions may correspond to a check symbol (vs. a data symbol). Configuration of the routing logic may occur at boot or initialization time. The configuration of the routing logic may be based upon error mapping information retrieved from system non-volatile memory (e.g., memory module serial presence detect information), or from memory tests performed during initialization. The configuration of the routing logic may be changed on a per-rank basis.

公开(公告)号：US11815940B2

公开(公告)日：2023-11-14

申请号：US17748762

申请日：2022-05-19

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  John Eric Linstadt ,  Thomas J. Giovannini ,  Kenneth L. Wright

IPC: G06F13/28 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02 ,  G11C5/02

CPC classification number: G06F13/287 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G06F2213/28

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

公开(公告)号：US20230359559A1

公开(公告)日：2023-11-09

申请号：US18203569

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12

CPC classification number: G06F12/0804 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/205 ,  G11C14/0018

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US11755220B2

公开(公告)日：2023-09-12

申请号：US17831576

申请日：2022-06-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G06F3/06 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/06 ,  G11C7/22 ,  G11C7/18 ,  G11C11/4097

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0655 ,  G06F3/0673 ,  G11C7/06 ,  G11C7/18 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097

Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

公开(公告)号：US11714752B2

公开(公告)日：2023-08-01

申请号：US17702505

申请日：2022-03-23

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12 ,  G11C14/00

CPC classification number: G06F12/0804 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/205 ,  G11C14/0018

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US11705187B2

公开(公告)日：2023-07-18

申请号：US17501311

申请日：2021-10-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  G11C7/02 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C11/4093 ,  G06F11/1048 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US11650944B2

公开(公告)日：2023-05-16

申请号：US17534125

申请日：2021-11-23

Applicant: Rambus Inc.

Inventor： John Eric Linstadt

IPC: G06F13/16 ,  G06F12/06 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G06F12/02

CPC classification number: G06F13/1694 ,  G06F12/0246 ,  G06F12/0623 ,  G06F12/0646 ,  G11C7/10 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22 ,  G06F13/1678 ,  G06F2212/7206

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

公开(公告)号：US11645152B2

公开(公告)日：2023-05-09

申请号：US17734464

申请日：2022-05-02

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Stephen Magee ,  John Eric Linstadt

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  G06F11/1048

Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

公开(公告)号：US11600316B2

公开(公告)日：2023-03-07

申请号：US17325977

申请日：2021-05-20

Applicant: Rambus Inc.

Inventor： Torsten Partsch ,  John Eric Linstadt ,  Helena Handschuh

IPC: G11C11/406 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/408

Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.