公开(公告)号：US20170054576A1

公开(公告)日：2017-02-23

申请号：US15259662

申请日：2016-09-08

Applicant: Rambus Inc.

Inventor： Qi Lin ,  Brian Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Kyung Suk Oh ,  Jared L. Zerbe

IPC: H04L25/03 ,  H04L12/26 ,  H04L7/00

CPC classification number: H04L25/03254 ,  H04L7/0025 ,  H04L7/0054 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/03057 ,  H04L25/03885 ,  H04L43/028 ,  H04L2025/03617

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

Abstract translation: 接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。 样本和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。 可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。

公开(公告)号：US09455825B2

公开(公告)日：2016-09-27

申请号：US14868721

申请日：2015-09-29

Applicant: Rambus Inc.

Inventor： Qi Lin ,  Brian Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Kyung Suk Oh ,  Jared L. Zerbe

IPC: H03H7/30 ,  H04L7/033 ,  H04L7/00 ,  H04L25/03

CPC classification number: H04L25/03254 ,  H04L7/0025 ,  H04L7/0054 ,  H04L7/0058 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0331 ,  H04L25/03057 ,  H04L25/03885 ,  H04L43/028 ,  H04L2025/03617

Abstract: A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

公开(公告)号：US20160209902A1

公开(公告)日：2016-07-21

申请号：US15012681

申请日：2016-02-01

Applicant: Rambus Inc.

Inventor： Yu Chang ,  Lei Luo ,  Kyung Suk Oh

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  H04B1/12 ,  H04L7/0054 ,  H04L7/033 ,  H04L25/03006 ,  H04L25/03012 ,  H04L25/03057 ,  H04L25/03127 ,  H04L25/03146 ,  H04L25/03853 ,  H04L2025/03433

Abstract: Disclosed embodiments relate to a system that changes transmitter and/or receiver settings to deal with reliability issues caused by a predetermined event, such as a change in a power state or a clock start event. One embodiment uses a first setting while operating a transmitter during a normal operating mode, and a second setting while operating the transmitter during a transient period following the predetermined event. A second embodiment uses similar first and second settings in a receiver, or in both a transmitter and a receiver employed on one side of a bidirectional link. The first and second settings can be associated with different swing voltages, edge rates, equalizations and/or impedances.

Abstract translation: 公开的实施例涉及改变发射机和/或接收机设置以处理由诸如功率状态或时钟启动事件的改变等预定事件引起的可靠性问题的系统。 一个实施例在正常操作模式期间操作发射机时使用第一设置，以及在预定事件之后的过渡期间操作发射机时的第二设置。 第二实施例在接收机中使用类似的第一和第二设置，或者在双向链路的一侧采用的发射机和接收机。 第一和第二设置可以与不同的摆动电压，边沿速率，均衡和/或阻抗相关联。

公开(公告)号：US20160005489A1

公开(公告)日：2016-01-07

申请号：US14857794

申请日：2015-09-17

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: G11C16/32 ,  G11C16/26

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: An IC die transmits command signals, address signals and data signals to a flash memory device at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within an array of non-volatile storage elements of the flash memory device. The IC die additionally transmits a control signal to the flash memory device via one or more external control signal lines, the control signal directing the flash memory device to switchably couple an on-die termination element to the time-multiplexed signaling line.

Abstract translation: IC芯片经由时间复用的外部信号线在各自的时间将命令信号，地址信号和数据信号发送到闪速存储器件，数据信号表示要存储在闪速存储器的非易失性存储元件阵列内的数据 设备。 IC芯片还经由一个或多个外部控制信号线将控制信号发送到闪速存储器件，该控制信号指示闪速存储器件可切换地将片上端接元件耦合到时分多路信号线。

公开(公告)号：US09225328B2

公开(公告)日：2015-12-29

申请号：US14696283

申请日：2015-04-24

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  H03K19/00 ,  H03K19/0175 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G06F13/40

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: In a non-volatile memory device having an array of non-volatile storage elements, command, address and data signals are received at respective times via a time-multiplexed external signaling line, the data signals representing data to be stored within the array of non-volatile storage elements. A control signal is received via a signaling path external to the non-volatile memory device, and an on-die termination element is switchably coupled to the time-multiplexed signaling line at least in part in response to a transition of the control signal from a first logic state to a second logic state.

Abstract translation: 在具有非易失性存储元件阵列的非易失性存储器件中，经由时间复用的外部信号线在各自的时间接收命令，地址和数据信号，该数据信号表示要存储在非阵列阵列内的数据 非易失存储元件。 经由非易失性存储器件外部的信令路径接收控制信号，并且片上终端元件至少部分地响应于来自控制信号的控制信号的转换而可切换地耦合到时间多路复用的信令线 第一逻辑状态到第二逻辑状态。

公开(公告)号：US09135206B2

公开(公告)日：2015-09-15

申请号：US14560357

申请日：2014-12-04

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K17/16 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  H03K19/00

CPC classification number: H03K19/0005 ,  G06F3/0605 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/4086 ,  G11C11/401 ,  G11C11/4063 ,  G11C11/4093 ,  G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  H03K19/017545

Abstract: An integrated circuit device transmits to a dynamic random access memory (DRAM) one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command. Thereafter, the integrated circuit device transmits to the DRAM a write command indicating that write data is to be sampled by a data interface of the DRAM during a first time interval and that cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval.

Abstract translation: 集成电路装置向动态随机存取存储器（DRAM）发送指定DRAM内数字控制值的编程的一个或多个命令，数字控制值指示DRAM要耦合到DRAM的数据接口的终端阻抗 DRAM响应于接收到写入命令并且在接收与写入命令相对应的写入数据期间，并且DRAM在接收到与写入命令相对应的写入数据之后与数据接口分离。 此后，集成电路装置向DRAM发送指示在第一时间间隔期间通过DRAM的数据接口对写入数据进行采样的写入命令，并且使得DRAM在第一时间间隔期间将终止阻抗耦合到数据接口 时间间隔，并在第一个时间间隔后将数据接口的终端阻抗解耦。

公开(公告)号：US08947962B2

公开(公告)日：2015-02-03

申请号：US14088277

申请日：2013-11-22

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C11/4063 ,  G11C29/02 ,  G11C5/04 ,  G11C11/4097 ,  G11C7/18 ,  G11C5/02

CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028

Abstract: A memory controller is disclosed. The memory controller is configured to be connected to one or more memory devices via an address and control (RQ) bus. Each of the memory devices have on-die termination (ODT) circuitry connected to a subset of signal lines of the RQ bus, and the memory controller is operable to selectively disable the ODT circuitry in at least one memory device of the one or more memory devices.

Abstract translation: 公开了一种存储器控制器。 存储器控制器被配置为经由地址和控制（RQ）总线连接到一个或多个存储器件。 每个存储器件具有连接到RQ总线的信号线子集的片上终端（ODT）电路，并且存储器控制器可操作地选择性地禁用该一个或多个存储器的至少一个存储器件中的ODT电路 设备。

公开(公告)号：US11349478B2

公开(公告)日：2022-05-31

申请号：US16940349

申请日：2020-07-27

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ian P. Shaeffer

IPC: H03K19/00 ,  G06F13/40 ,  G11C11/4093 ,  H03K19/0175 ,  G11C11/401 ,  G11C11/419 ,  G11C16/26 ,  G11C11/41 ,  G11C11/4063 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G11C16/32 ,  G06F3/06

Abstract: In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

公开(公告)号：US11083077B2

公开(公告)日：2021-08-03

申请号：US16860805

申请日：2020-04-28

Applicant: Rambus Inc.

Inventor： Kyung Suk Oh ,  Ralf M. Schmitt ,  Yijiong Feng

IPC: H05K7/00 ,  H05K1/02 ,  H01L23/498 ,  H01L23/528 ,  H01B5/02 ,  H01L23/522

Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.

公开(公告)号：US20210225417A1

公开(公告)日：2021-07-22

申请号：US17222388

申请日：2021-04-05

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C7/22 ,  G11C5/06 ,  G11C29/02 ,  G11C11/4063

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A memory controller sends register values, for storage in a plurality of registers of a respective memory device. The register values include register values that represent one or more impedance values of on-die termination (ODT) impedances to apply to the respective inputs of the respective memory device that receive the CA signals, and one or more register values to selectively enable application of a chip select ODT impedance to the chip select input of the respective memory device.