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公开(公告)号：US11948916B2
公开(公告)日：2024-04-02
申请号：US17507271
申请日：2021-10-21
发明人： Shuuichi Kariyazaki
IPC分类号： H01L25/065 , H01L23/00 , H01L23/498 , H01L23/538
CPC分类号： H01L25/0655 , H01L23/49822 , H01L23/5383 , H01L24/16 , H01L24/17 , H01L2223/6638 , H01L2224/16235 , H01L2224/17515 , H01L2924/381
摘要： The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction.
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12.发明授权公开(公告)号：US11605581B2
公开(公告)日：2023-03-14
申请号：US17144897
申请日：2021-01-08
发明人： Wataru Shiroi , Shuuichi Kariyazaki
IPC分类号： H01L23/498 , H01L23/00
摘要： A semiconductor device comprising a wiring member with which a semiconductor chip is electrically connected including: a first wiring layer having a plurality of first conductive patterns; a second wiring layer arranged next to the first wiring layer in a thickness direction of the wiring member, and having a second conductive pattern; and a third wiring layer arranged next to the second wiring layer in the thickness direction of the wiring member, and having a third conductive pattern. Here, in plan view, a first opening portion of each of two, which are arranged next to each other, of a plurality of first opening portions each penetrating through the second conductive pattern is overlapped with a pair of differential signal wirings contained in plurality of first conductive patterns, and is overlapped with two or more of a plurality of second opening portions each penetrating through the third conductive pattern.
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公开(公告)号：US10541216B2
公开(公告)日：2020-01-21
申请号：US16175522
申请日：2018-10-30
发明人： Kazuyuki Nakagawa , Keita Tsuchiya , Yoshiaki Sato , Shuuichi Kariyazaki , Norio Chujo , Masayoshi Yagyu , Yutaka Uematsu
IPC分类号： H01L27/146 , H01L23/66 , H01L23/538 , H01L23/367 , H01L23/00
摘要： A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.
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公开(公告)号：US09917026B2
公开(公告)日：2018-03-13
申请号：US15515465
申请日：2014-12-24
IPC分类号： H01L23/48 , H01L23/14 , H01L23/498 , H01L25/065 , H01L23/66
CPC分类号： H01L23/147 , H01L23/00 , H01L23/32 , H01L23/498 , H01L23/49811 , H01L23/49816 , H01L23/49894 , H01L23/50 , H01L23/5383 , H01L23/5384 , H01L23/66 , H01L25/065 , H01L25/0655 , H01L25/07 , H01L25/18 , H01L2223/6611 , H01L2223/6638 , H01L2224/16225 , H01L2225/06506 , H01L2225/06517 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.
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公开(公告)号：US09853002B2
公开(公告)日：2017-12-26
申请号：US15295094
申请日：2016-10-17
发明人： Shuuichi Kariyazaki
IPC分类号： H01L23/64 , H01L23/66 , H01L23/498 , H05K1/02 , H01L23/538 , H01L23/50 , H01L23/522 , H05K1/18
CPC分类号： H01L23/642 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/50 , H01L23/5222 , H01L23/5383 , H01L23/66 , H01L2223/6627 , H01L2223/6661 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311 , H01L2924/30111 , H05K1/0231 , H05K1/181 , H05K2201/10378
摘要： A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer.
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公开(公告)号：US09620447B2
公开(公告)日：2017-04-11
申请号：US15059948
申请日：2016-03-03
IPC分类号： H01L23/498 , H05K1/02 , H01L23/522 , H01L23/00
CPC分类号： H01L23/49822 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5225 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/0401 , H01L2224/05082 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05644 , H01L2224/05655 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/14135 , H01L2224/16057 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81815 , H01L2224/83104 , H01L2924/1517 , H01L2924/15311 , H05K1/0225 , H05K1/0253 , H05K2201/09336 , H05K2201/09681 , H01L2924/014 , H01L2924/00014 , H01L2924/00
摘要： To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.
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公开(公告)号：US09461016B2
公开(公告)日：2016-10-04
申请号：US14967463
申请日：2015-12-14
IPC分类号： H01L25/065 , H01L23/498
CPC分类号： H01L25/0655 , H01L23/147 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/5226 , H01L23/528 , H01L24/13 , H01L24/16 , H01L25/18 , H01L2224/0401 , H01L2224/13022 , H01L2224/16227 , H01L2224/16235 , H01L2225/06506 , H01L2225/0651 , H01L2225/06555 , H01L2924/1431 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/3025 , H01L2924/0002 , H01L2924/00
摘要： To improve reliability of signal transmission of an interposer which couples between semiconductor chips. A reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a first wiring layer of an interposer. Also, a reference potential wiring and a reference potential wiring are provided on both neighboring sides of a signal wiring provided in a second wiring layer of the interposer. Further, the signal wiring and the signal wiring cross each other in plan view. The reference potential wirings of the first wiring layer, and the reference potential wirings of the second wiring layer are coupled to each other at the periphery of their crossing portion.
摘要翻译： 为了提高耦合在半导体芯片之间的插入器的信号传输的可靠性。 在设置在插入件的第一布线层中的信号线的两个相邻侧上设置参考电位布线和参考电位布线。 此外，在设置在插入器的第二布线层中的信号线的两个相邻侧上设置参考电位布线和参考电位布线。 此外，信号布线和信号布线在平面图中彼此交叉。 第一布线层的参考电位布线和第二布线层的参考电位布线在其交叉部分的周围彼此耦合。
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公开(公告)号：US11158597B2
公开(公告)日：2021-10-26
申请号：US16817172
申请日：2020-03-12
发明人： Wataru Shiroi , Shuuichi Kariyazaki
摘要： The electronic device includes first and second semiconductor components. And, the electronic device includes a sealing body for sealing the first semiconductor component (i.e., the logic chip). A plurality of through conductors electrically connected to the first semiconductor component and/or the second semiconductor component is formed in the sealing body. In plan view, the sealing body has a first region in which the first semiconductor component is located, a second region located on a periphery of a first surface of the sealing body, a third region located between the second region and the first region, and a fourth region located between the second region and the third region. The plurality of through conductors is arranged most in the second region. The number of the plurality of through conductors located in the third region is larger than the number of the plurality of through conductors located in the fourth region.
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公开(公告)号：US11101206B2
公开(公告)日：2021-08-24
申请号：US16653098
申请日：2019-10-15
IPC分类号： H01L23/498 , H01L25/16 , H01L23/00 , H01L23/64 , H01L23/50 , H01L23/367
摘要： The lower surface of the wiring substrate includes a first region overlapping with the semiconductor chip mounted on the upper surface, and a second region surrounding the first region and not overlapping with the semiconductor chip. The first region includes a third region in which the plurality of external terminals is not arranged, and a fourth region surrounding the third region in which the plurality of external terminals is arranged. The plurality of external terminals includes a plurality of terminals arranged in the fourth region of the first region and a plurality of terminals arranged in the second region. The plurality of terminals includes a plurality of power supply terminals for supplying a power supply potential to the core circuit of the semiconductor chip, and a plurality of reference terminals for supplying a reference potential to the core circuit of the semiconductor chip.
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公开(公告)号：US10515890B2
公开(公告)日：2019-12-24
申请号：US15817267
申请日：2017-11-19
IPC分类号： H01L21/66 , H01L23/498 , H01L23/64 , H01L23/31 , H01L23/367 , H01L21/48 , H01L21/56 , H01L25/065 , H05K1/02 , H01L23/50 , H01L23/00 , H05K1/18 , H05K3/46
摘要： A semiconductor device which provides improved reliability. The semiconductor device includes: a wiring substrate having a first surface and a second surface opposite to the first surface; a chip condenser built in the wiring substrate, having a first electrode and a second electrode; a first terminal and a second terminal disposed on the first surface; and a third terminal disposed on the second surface. The semiconductor device further includes: a first conduction path for coupling the first terminal and the third terminal; a second conduction path for coupling the first terminal and the first electrode; a third conduction path for coupling the third terminal and the first electrode; and a fourth conduction path for coupling the second terminal and the first electrode.
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