公开(公告)号：US10541216B2

公开(公告)日：2020-01-21

申请号：US16175522

申请日：2018-10-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuyuki Nakagawa ,  Keita Tsuchiya ,  Yoshiaki Sato ,  Shuuichi Kariyazaki ,  Norio Chujo ,  Masayoshi Yagyu ,  Yutaka Uematsu

IPC: H01L27/146 ,  H01L23/66 ,  H01L23/538 ,  H01L23/367 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.

公开(公告)号：US10304768B2

公开(公告)日：2019-05-28

申请号：US15989771

申请日：2018-05-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuyuki Nakagawa ,  Shinji Baba ,  Takeumi Kato

IPC: H01L23/498 ,  H01L25/00 ,  H05K3/46 ,  H01L21/56 ,  H01L21/66 ,  H01L23/31 ,  H01L23/367 ,  H01L23/66 ,  H01L23/00 ,  H01L23/50 ,  H05K1/02

Abstract: A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer.

公开(公告)号：US20160111388A1

公开(公告)日：2016-04-21

申请号：US14983753

申请日：2015-12-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji Baba ,  Masaki Watanabe ,  Muneharu Tokunaga ,  Kazuyuki Nakagawa

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/291 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/1134 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13075 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14136 ,  H01L2224/14155 ,  H01L2224/14177 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced.

Abstract translation: 提供了能够提高半导体器件的可靠性的技术。 在本发明中，作为安装有半导体芯片的布线基板，不使用积层布线板，而是使用贯通布线板THWB。 以这种方式，在本发明中，仅使用芯层形成的贯通布线板，因此不需要考虑堆积层与芯层之间的热膨胀系数的差异， 不需要考虑由于积聚层不存在而在积层中形成的精细通孔的电断开。 结果，根据本发明，可以提高半导体器件的可靠性，同时降低成本。

公开(公告)号：US10763214B2

公开(公告)日：2020-09-01

申请号：US16405644

申请日：2019-05-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shuuichi Kariyazaki ,  Kazuyuki Nakagawa ,  Keita Tsuchiya ,  Yosuke Katsura ,  Shinji Katayama ,  Norio Chujo ,  Masayoshi Yagyu ,  Yutaka Uematsu

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/498 ,  H05K1/02 ,  H04L25/02

Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.

公开(公告)号：US10396044B2

公开(公告)日：2019-08-27

申请号：US15759211

申请日：2015-10-15

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki Nakagawa ,  Keita Tsuchiya ,  Yoshiaki Sato ,  Shinji Baba

IPC: H01L23/495 ,  H01L23/64 ,  H01L23/12 ,  H01L25/00 ,  H05K3/46 ,  H01L21/48 ,  H01L21/66 ,  H01L23/16 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01G4/38 ,  H01G4/40 ,  H05K1/02 ,  H05K1/18 ,  H01L23/36 ,  H01L23/50 ,  H01G2/06 ,  G01R31/28

Abstract: A semiconductor device includes a wiring substrate including a first surface and a second surface opposite to the first surface, a semiconductor chip including a plurality of chip electrodes and mounted over the wiring substrate, a first capacitor arranged at a position overlapping with the semiconductor chip in plan view and incorporated in the wiring substrate, and a second capacitor arranged between the first capacitor and a peripheral portion of the wiring substrate in plan view. Also, the second capacitor is inserted in series connection into a signal transmission path through which an electric signal is input to or output from the semiconductor chip.

公开(公告)号：US10037966B2

公开(公告)日：2018-07-31

申请号：US15375072

申请日：2016-12-09

Applicant: Renesas Electronics Corporation

Inventor： Toshihiro Iwasaki ,  Takeumi Kato ,  Takanori Okita ,  Yoshikazu Shimote ,  Shinji Baba ,  Kazuyuki Nakagawa ,  Michitaka Kimura

IPC: H01L23/00 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11 ,  H01L21/48 ,  H01L21/56 ,  H01L25/075

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/75 ,  H01L24/83 ,  H01L24/94 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/056 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2224/14131 ,  H01L2224/1605 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/75745 ,  H01L2224/75824 ,  H01L2224/8101 ,  H01L2224/81024 ,  H01L2224/81048 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/831 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2224/81201 ,  H01L2924/00

Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.

公开(公告)号：US11049806B2

公开(公告)日：2021-06-29

申请号：US16370370

申请日：2019-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuyuki Nakagawa ,  Shinji Baba ,  Hiroshi Koizumi

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L23/482 ,  H01L23/498 ,  H01L23/52 ,  H01L23/538 ,  H01L23/532 ,  H01L23/34 ,  H01L23/00

Abstract: A semiconductor device includes a wiring substrate provided with a plurality of pads electrically connected to a semiconductor chip in a flip-chip interconnection. The wiring substrate includes a pad forming layer in which a signal pad configured to receive transmission of a first signal and a second pad configured to receive transmission of a second signal different from the first signal are formed and a first wiring layer located at a position closest to the pad forming layer. In the wiring layer, a via land overlapping with the signal pad, a wiring connected to the via land, and a wiring connected to the second pad and extending in an X direction are formed. In a Y direction intersecting the X direction, a width of the via land is larger than a width of the wiring. A wiring is adjacent to the via land and overlaps with the signal pad.

公开(公告)号：US10325841B2

公开(公告)日：2019-06-18

申请号：US16063280

申请日：2016-02-10

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki Nakagawa ,  Katsushi Terajima ,  Keita Tsuchiya ,  Yoshiaki Sato ,  Hiroyuki Uchida ,  Yuji Kayashima ,  Shuuichi Kariyazaki ,  Shinji Baba

IPC: H01L23/52 ,  H01L23/498 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L23/538 ,  H01L23/00

Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member. In addition, the first terminal of the first semiconductor component is electrically connected to the wiring substrate via a first bump electrode without the first wiring member interposed therebetween.

公开(公告)号：US10056323B2

公开(公告)日：2018-08-21

申请号：US15302632

申请日：2014-04-24

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki Nakagawa ,  Shinji Baba ,  Takeumi Kato

IPC: H01L23/52 ,  H01L23/498 ,  H01L25/00 ,  H05K3/46 ,  H01L21/56 ,  H01L21/66 ,  H01L23/31 ,  H01L23/367 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/56 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/00 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0225 ,  H05K1/0231 ,  H05K1/0253 ,  H05K3/46 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer.

公开(公告)号：US09330992B2

公开(公告)日：2016-05-03

申请号：US14196736

申请日：2014-03-04

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki Nakagawa

IPC: H01L23/48 ,  H01L23/12 ,  H01L23/498 ,  H01L23/50 ,  H05K1/11 ,  H01L23/367 ,  H05K1/02 ,  H01L23/00

CPC classification number: H01L23/12 ,  H01L23/367 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0253 ,  H05K1/116 ,  H05K2201/09309 ,  H05K2201/09718 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/05432 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device is provided with improved resistance to noise. Conductive planes are respectively formed over wiring layers. One wiring layer is provided with a through hole land integrally formed with a through hole wiring. In other wiring layers located over the wiring layer with the through hole land, openings are respectively formed in the conductive planes. The area of each of the openings is larger than the plane area of the through hole land.

Abstract translation: 半导体器件具有改善的抗噪声能力。 导电平面分别形成在布线层上。 一个布线层设置有与通孔布线一体形成的通孔区域。 在位于具有通孔焊盘的布线层上方的其它布线层中，在导电平面中分别形成开口。 每个开口的面积大于通孔平台的平面面积。