公开(公告)号：US09917026B2

公开(公告)日：2018-03-13

申请号：US15515465

申请日：2014-12-24

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi Oikawa ,  Toshihiko Ochiai ,  Shuuichi Kariyazaki ,  Yuji Kayashima ,  Tsuyoshi Kida

IPC: H01L23/48 ,  H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H01L23/66

CPC classification number: H01L23/147 ,  H01L23/00 ,  H01L23/32 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/66 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

公开(公告)号：US20190189601A1

公开(公告)日：2019-06-20

申请号：US16146881

申请日：2018-09-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuji Kayashima

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/214 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/92125 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: The characteristics of an electronic device can be improved. The electronic device includes a first redistribution layer formed over an upper surface US of a sealing body, and a second redistribution layer formed below a bottom surface of the sealing body. The thickness of the second redistribution layer is smaller than the thickness of the first redistribution layer.

公开(公告)号：US10325841B2

公开(公告)日：2019-06-18

申请号：US16063280

申请日：2016-02-10

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki Nakagawa ,  Katsushi Terajima ,  Keita Tsuchiya ,  Yoshiaki Sato ,  Hiroyuki Uchida ,  Yuji Kayashima ,  Shuuichi Kariyazaki ,  Shinji Baba

IPC: H01L23/52 ,  H01L23/498 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L23/538 ,  H01L23/00

Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member. In addition, the first terminal of the first semiconductor component is electrically connected to the wiring substrate via a first bump electrode without the first wiring member interposed therebetween.

公开(公告)号：US10347552B2

公开(公告)日：2019-07-09

申请号：US15879610

申请日：2018-01-25

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi Oikawa ,  Toshihiko Ochiai ,  Shuuichi Kariyazaki ,  Yuji Kayashima ,  Tsuyoshi Kida

IPC: H01L23/14 ,  H01L23/00 ,  H01L23/32 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L23/498 ,  H01L23/66 ,  H01L23/538 ,  H01L23/50

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

公开(公告)号：US10297547B2

公开(公告)日：2019-05-21

申请号：US15861261

申请日：2018-01-03

Applicant: Renesas Electronics Corporation

Inventor： Yuji Kayashima ,  Tomohisa Sekiguchi

IPC: H01L23/528 ,  H01L23/00

Abstract: A wiring is formed over a semiconductor substrate via an interlayer insulation film, and another interlayer insulation film is formed over the interlayer insulation film so as to cover the wiring, and a pad is formed over the another interlayer insulation film. Over the another interlayer insulation film, a layered film having an opening portion in which a pad is exposed is formed, and a redistribution wiring electrically connected to the pad is formed over the layered film and over the pad exposed in the opening portion. An end portion of the wiring is located below a connection region between the pad and the redistribution wiring. The wiring has a plurality of opening portions formed therein, and at least a part of the plurality of opening portions overlaps with the connection region in plan view.

公开(公告)号：US20180247893A1

公开(公告)日：2018-08-30

申请号：US15861261

申请日：2018-01-03

Applicant: Renesas Electronics Corporation

Inventor： Yuji Kayashima ,  Tomohisa Sekiguchi

IPC: H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5283 ,  H01L23/5223 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5286 ,  H01L24/04 ,  H01L24/13 ,  H01L2224/0236 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/13024 ,  H01L2924/3512

Abstract: A wiring is formed over a semiconductor substrate via an interlayer insulation film, and another interlayer insulation film is formed over the interlayer insulation film so as to cover the wiring, and a pad is formed over the another interlayer insulation film. Over the another interlayer insulation film, a layered film having an opening portion in which a pad is exposed is formed, and a redistribution wiring electrically connected to the pad is formed over the layered film and over the pad exposed in the opening portion. An end portion of the wiring is located below a connection region between the pad and the redistribution wiring. The wiring has a plurality of opening portions formed therein, and at least a part of the plurality of opening portions overlaps with the connection region in plan view.