公开(公告)号：US20190391325A1

公开(公告)日：2019-12-26

申请号：US16438067

申请日：2019-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: G02B6/036 ,  G02B6/42

Abstract: The semiconductor device includes an optical waveguide WG1 formed in a planar manner, and a three-dimensional optical waveguide WG2 optically connected with the optical waveguide WG1 and including a curved shape.

公开(公告)号：US20190273066A1

公开(公告)日：2019-09-05

申请号：US16278927

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi KUWABARA ,  Yasutaka NAKASHIBA ,  Tetsuya IIDA

IPC: H01L25/065 ,  H02K11/33 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L49/02

Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.

公开(公告)号：US20180180827A1

公开(公告)日：2018-06-28

申请号：US15832795

申请日：2017-12-06

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya IIDA ,  Yasutaka Nakashiba

IPC: G02B6/42 ,  H01S5/022 ,  H01S5/042 ,  H01S5/02 ,  G02B6/13 ,  G02B6/12 ,  G02B6/30

CPC classification number: G02B6/4239 ,  G02B6/12004 ,  G02B6/13 ,  G02B6/30 ,  G02B6/4204 ,  G02B6/4232 ,  G02B2006/12061 ,  G02B2006/12121 ,  G02B2006/12123 ,  H01S5/005 ,  H01S5/021 ,  H01S5/02228 ,  H01S5/0224 ,  H01S5/02252 ,  H01S5/02272 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/024 ,  H01S5/0425

Abstract: A Si photonics device includes: a first semiconductor chip; a second semiconductor chip having a laser diode and mounted on the first semiconductor chip; a third semiconductor chip taking in a laser beam emitted from the laser diode and mounted on the first semiconductor chip; and a resin layer disposed on the first semiconductor chip so as to face the second semiconductor chip. Further, the Si photonics device has: a bump electrode connecting the second semiconductor chip and an upper layer electrode pad provided on the resin layer of the first semiconductor chip; and a bump electrode connecting the first semiconductor chip and the third semiconductor chip, and the second semiconductor chip is mounted on the first semiconductor chip via the resin layer.

公开(公告)号：US20180128974A1

公开(公告)日：2018-05-10

申请号：US15729727

申请日：2017-10-11

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: G02B6/122 ,  G02B6/136

CPC classification number: G02B6/122 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12142 ,  G02F1/011 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/1203

Abstract: A semiconductor device includes: a first substrate; a surface insulating film formed over an upper surface of the first substrate; a BOX layer formed over the surface insulating film; an optical waveguide made of an SOI layer formed on the BOX layer; and a first interlayer insulating film formed over the BOX layer so as to cover the optical waveguide. The semiconductor device further includes: a trench formed in the surface insulating film and the first substrate below the optical waveguide; and a cladding layer made of a buried insulating film buried in the trench. A thickness of the BOX layer is 1 μm or less, and a distance from an interface between the optical waveguide and the BOX layer to a bottom surface of the trench is 2 μm or more.

公开(公告)号：US20160247915A1

公开(公告)日：2016-08-25

申请号：US15146766

申请日：2016-05-04

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya IIDA

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/7824 ,  H01L21/30625 ,  H01L21/743 ,  H01L21/76243 ,  H01L21/76248 ,  H01L21/76283 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a supporting substrate, an insulating film formed in a first region over the supporting substrate, a first semiconductor layer formed over the insulating film, a first epitaxial layer formed in an opening of the insulating film in a second region over the supporting substrate, an element isolation region formed between the first semiconductor layer and the first epitaxial layer, and a semiconductor element formed over each of the first semiconductor layer in the first region and the first epitaxial layer in the second region. The first semiconductor layer and the first epitaxial layer is spaced apart from each other by 5 μm or more.

Abstract translation: 半导体器件包括支撑衬底，形成在支撑衬底上的第一区域中的绝缘膜，形成在绝缘膜上的第一半导体层，形成在第二区域中的绝缘膜的开口中的第一外延层， 衬底，形成在第一半导体层和第一外延层之间的元件隔离区，以及形成在第一区域中的第一半导体层和第二区域中的第一外延层之上的半导体元件。 第一半导体层和第一外延层彼此间隔开5μm以上。

公开(公告)号：US20210167012A1

公开(公告)日：2021-06-03

申请号：US16700485

申请日：2019-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunji KUBO ,  Koichi ANDO ,  Eiji IO ,  Hideyuki TAJIMA ,  Tetsuya IIDA

IPC: H01L23/522 ,  H01L23/373

Abstract: A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.

公开(公告)号：US20180308795A1

公开(公告)日：2018-10-25

申请号：US15953872

申请日：2018-04-16

Applicant: Renesas Electronics Corporation

Inventor： Shinichi UCHIDA ,  Yasutaka NAKASHIBA ,  Tetsuya IIDA ,  Shinichi KUWABARA

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/3213

Abstract: A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.

公开(公告)号：US20180299706A1

公开(公告)日：2018-10-18

申请号：US15878619

申请日：2018-01-24

Applicant: Renesas Electronics Corporation

Inventor： Shinichi KUWABARA ,  Yasutaka NAKASHIBA ,  Tetsuya IIDA ,  Shinichi WATANUKI

IPC: G02F1/025 ,  H01L29/06 ,  H01L29/16 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/02

CPC classification number: G02F1/025 ,  G02F2001/0151 ,  G02F2201/302 ,  G02F2202/105 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/0657 ,  H01L29/16

Abstract: To reduce a production cost of a semiconductor device and provide a semiconductor device having improved characteristics. A grating coupler has a plurality of projections separated from each other in an optical waveguide direction and a slab portion formed between any two of the projections adjacent to each other and formed integrally with them; a MOS optical modulator has a projection extending in the optical waveguide direction and slab portions formed on both sides of the projection, respectively, and formed integrally therewith. The projection of the grating coupler and the MOS optical modulator is formed of a first semiconductor layer, a second insulating layer, and a second semiconductor layer stacked successively on a first insulating layer, while the grating coupler and the MOS optical modulator each have a slab portion formed of the first semiconductor layer.

公开(公告)号：US20180158910A1

公开(公告)日：2018-06-07

申请号：US15869023

申请日：2018-01-11

Applicant: Renesas Electronics Corporation

Inventor： Yuya ABIKO ,  Satoshi EGUCHI ,  Akio ICHIMURA ,  Natsuo YAMAGUCHI ,  Tetsuya IIDA

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/08

CPC classification number: H01L21/38 ,  H01L21/76237 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/0688 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66727 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7811

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

公开(公告)号：US20160268369A1

公开(公告)日：2016-09-15

申请号：US14968004

申请日：2015-12-14

Applicant: Renesas Electronics Corporation

Inventor： Akio ICHIMURA ,  Satoshi EGUCHI ,  Tetsuya IIDA ,  Yuya ABIKO

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7811

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

Abstract translation: 形成具有高纵横比的超结结构。 外延层使用沟槽填充工艺分层地形成，并且当已经形成每个层时，在该层中形成沟槽。 例如，当已经形成第一外延层时，在外延层中形成第一沟槽。 随后，当已经形成第二外延层时，在外延层中形成第二沟槽。 随后，当形成第三外延层时，在第三外延层中形成第三沟槽。