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公开(公告)号：US09362932B2
公开(公告)日：2016-06-07
申请号：US14817645
申请日：2015-08-04
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Keisuke Kimura , Yuichi Okuda , Hideo Nakane , Takaya Yamamoto
CPC classification number: H03M1/0634 , H03M1/002 , H03M1/0617 , H03M1/1009 , H03M1/12 , H03M1/1215 , H03M1/1225
Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.
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公开(公告)号：US09300248B2
公开(公告)日：2016-03-29
申请号：US14263030
申请日：2014-04-28
Applicant: Renesas Electronics Corporation
Inventor： Osamu Ozawa , Masashi Horiguchi , Yuichi Okuda , Akihito Anzai
CPC classification number: H03B5/32 , H02H7/20 , H03B5/364 , H03B2200/0088 , H03B2202/03 , H03B2202/082 , H03B2202/084 , H05K1/181 , H05K2201/10075
Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
Abstract translation: 用于振荡输入信号的布线图案和用于振荡输出信号的布线图案设置在印刷电路板上，并且用于接地电源电压的布线图案布置在它们之间的区域中。 在用于振荡输入信号的布线图案和振荡输出信号的布线图案之间连接石英晶体单元，并且将其作为负载电容器的电容器的一端连接到地电源电压的布线图案。 此外，为了包围这些布线图案，布置有用于VSS的布线图案，并且除此之外，还布置有用于VSS的布线图案。 通过这种方式，可以实现XIN节点和XOUT节点之间的寄生电容的减小，这些节点等的噪声容限的改善。
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公开(公告)号：US09258006B2
公开(公告)日：2016-02-09
申请号：US14711733
申请日：2015-05-13
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Takashi Oshima , Tatsuji Matsuura , Yuichi Okuda , Hideo Nakane , Takaya Yamamoto , Keisuke Kimura
CPC classification number: H03M1/1245 , H03M1/002 , H03M1/0609 , H03M1/0639 , H03M1/1038 , H03M1/109 , H03M1/14 , H03M1/38 , H03M1/44 , H03M1/46 , H03M1/56
Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.
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14.发明授权Semiconductor device having analog-to-digital converter with gain-dependent dithering and communication apparatus 有权具有与增益相关的抖动和通信装置的模数转换器的半导体器件公开(公告)号：US08823565B2
公开(公告)日：2014-09-02
申请号：US13940819
申请日：2013-07-12
Applicant: Renesas Electronics Corporation
Inventor： Keisuke Kimura , Tatsuji Matsuura , Yuichi Okuda , Hideo Nakane , Takaya Yamamoto
IPC: H03M1/20
CPC classification number: H03M3/49 , H03M1/201 , H03M3/328 , H03M3/332 , H03M3/43 , H03M3/438 , H03M3/486
Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.
Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。
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公开(公告)号：US10020814B2
公开(公告)日：2018-07-10
申请号：US15594753
申请日：2017-05-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Keisuke Kimura , Yuichi Okuda , Hideo Nakane , Takaya Yamamoto
CPC classification number: H03M1/0634 , H03M1/002 , H03M1/0617 , H03M1/1009 , H03M1/12 , H03M1/1215 , H03M1/1225
Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.
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Patent Agency Ranking
公开(公告)号：US09685968B2
公开(公告)日：2017-06-20
申请号：US15142273
申请日：2016-04-29
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Keisuke Kimura , Yuichi Okuda , Hideo Nakane , Takaya Yamamoto
CPC classification number: H03M1/0634 , H03M1/002 , H03M1/0617 , H03M1/1009 , H03M1/12 , H03M1/1215 , H03M1/1225
Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.
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公开(公告)号：US09184755B2
公开(公告)日：2015-11-10
申请号：US14487179
申请日：2014-09-16
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Keisuke Kimura , Yuichi Okuda , Hideo Nakane , Takaya Yamamoto
CPC classification number: H03M1/0607 , H01L23/5225 , H01L23/5226 , H01L23/528 , H01L27/0629 , H01L2924/0002 , H03M1/0604 , H03M1/1023 , H03M1/124 , H03M1/1245 , H03M1/442 , H03M1/46 , H03M1/462 , H03M1/468 , H01L2924/00
Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.
Abstract translation: 根据本发明的一个方面的半导体器件涉及通过使用比较器将模拟信号的信号电平转换为数字值的AD转换器，并且基于偏移来确定比较器的偏移电压的调整量 在作为转换结果的数字值输出的最低有效位（LSB）之后立即获得的比较器的确定结果被转换。
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18.发明申请Semiconductor Device Having Analog-To-Digital Converter With Gain-Dependent Dithering And Communication Apparatus 有权具有增益依赖抖动和通信设备的模数转换器的半导体器件公开(公告)号：US20140333461A1
公开(公告)日：2014-11-13
申请号：US14445682
申请日：2014-07-29
Applicant: Renesas Electronics Corporation
Inventor： Keisuke Kimura , Yuichi Okuda , Hideo Nakane , Takaya Yamamoto , Tatsuji Matsuura
CPC classification number: H03M3/49 , H03M1/201 , H03M3/328 , H03M3/332 , H03M3/43 , H03M3/438 , H03M3/486
Abstract: A semiconductor communication device reduces influence of noise that is produced by applying a dither signal. The semiconductor communication device includes a Delta-Sigma analog-to-digital converter that converts input analog signals to digital signals, a power detecting unit that detects signal power of the digital signals, a gain control unit that changes a gain setting of analog signals to be input to the Delta-Sigma analog-to-digital converter depending on the signal power of the digital signals, and a dither signal control unit that causes the Delta-Sigma analog-to-digital converter to selectively add the dither signal when the gain setting changes.
Abstract translation: 半导体通信设备减少通过应用抖动信号产生的噪声的影响。 该半导体通信装置包括将输入的模拟信号转换为数字信号的Delta-Sigma模数转换器，检测数字信号的信号功率的功率检测单元，将模拟信号的增益设定变更为 根据数字信号的信号功率输入到Delta-Sigma模数转换器;以及抖动信号控制单元，其使Delta-Sigma模数转换器在增益时选择性地添加抖动信号 设置更改。
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公开(公告)号：US20140232476A1
公开(公告)日：2014-08-21
申请号：US14263030
申请日：2014-04-28
Applicant: Renesas Electronics Corporation
Inventor： Osamu Ozawa , Masashi Horiguchi , Yuichi Okuda , Akihito Anzai
CPC classification number: H03B5/32 , H02H7/20 , H03B5/364 , H03B2200/0088 , H03B2202/03 , H03B2202/082 , H03B2202/084 , H05K1/181 , H05K2201/10075
Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
Abstract translation: 用于振荡输入信号的布线图案和用于振荡输出信号的布线图案设置在印刷电路板上，并且用于接地电源电压的布线图案布置在它们之间的区域中。 在用于振荡输入信号的布线图案和振荡输出信号的布线图案之间连接石英晶体单元，并且其作为负载电容器的电容器的一端连接到地电源电压的布线图案。 此外，为了包围这些布线图案，布置有用于VSS的布线图案，并且除此之外，还布置有用于VSS的布线图案。 通过这种方式，可以实现XIN节点和XOUT节点之间的寄生电容的减小，这些节点等的噪声容限的改善。
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20.发明授权公开(公告)号：US09678526B2
公开(公告)日：2017-06-13
申请号：US14669352
申请日：2015-03-26
Applicant: Renesas Electronics Corporation
Inventor： Atsushi Motozawa , Yuichi Okuda
Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.
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