公开(公告)号：US20150061145A1

公开(公告)日：2015-03-05

申请号：US14534247

申请日：2014-11-06

Applicant: ROHM CO., LTD.

Inventor： Yuichi NAKAO ,  Satoshi KAGEYAMA ,  Masaru NAITOU

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  B23D51/125 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/05 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

Abstract translation: 根据本发明的半导体器件包括半导体衬底，层叠在半导体衬底上的第一绝缘层，嵌入在第一绝缘层的引线形成区域中的第一金属布线图案，层压在第一绝缘层上的第二绝缘层 层，嵌入在第二绝缘层的线形成区域中的第二金属布线图案和嵌入在与第二绝缘层的线形成区域相对的线对向区域中的第一虚拟金属图案，并且以非线 与第二绝缘层的线形成区域以外的非线形成区域相对的相对区域，线对向区域和非线对置区域各自位于除非线形成区域以外的非线形成区域 第一绝缘层的线形成区域。

公开(公告)号：US20230298805A1

公开(公告)日：2023-09-21

申请号：US18300193

申请日：2023-04-13

Applicant: ROHM CO., LTD.

Inventor： Kosei OSADA ,  Isamu NISHIMURA ,  Tetsuya KAGAWA ,  Daiki YANAGISHIMA ,  Toshiyuki ISHIKAWA ,  Michihiko MIFUJI ,  Satoshi KAGEYAMA ,  Nobuyuki KASAHARA

IPC: H01F27/28 ,  H01L23/64 ,  H01L23/522 ,  H01L23/58 ,  H01L23/495

CPC classification number: H01F27/288 ,  H01F27/2804 ,  H01L23/49575 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L23/645 ,  H01L23/3107

Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

公开(公告)号：US20230092639A1

公开(公告)日：2023-03-23

申请号：US17820306

申请日：2022-08-17

Applicant: ROHM CO., LTD.

Inventor： Satoshi KAGEYAMA

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor device includes: a conductive portion; and a semiconductor element mounted on the conductive portion, wherein the conductive portion is made of a plating layer, wherein the conductive portion includes a mounting portion having a mounting surface on which the semiconductor element is mounted, and a terminal portion extending to an opposite side of the semiconductor element with respect to the mounting portion, wherein the mounting portion extends in a first direction along the mounting surface more than the terminal portion, and wherein the mounting portion and the terminal portion are integrally formed.

公开(公告)号：US20220139815A1

公开(公告)日：2022-05-05

申请号：US17511274

申请日：2021-10-26

Applicant: ROHM CO., LTD.

Inventor： Satoshi KAGEYAMA

IPC: H01L23/498 ,  H01L23/14 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure relates to a semiconductor device and a method manufacturing thereof. The object of the present disclosure is to simplify manufacturing steps of a semiconductor device. A semiconductor device of the present disclosure includes an organic film electrically insulative and penetrated by a through hole in a thickness direction, a conductive layer formed on the organic film and made of a copper (Cu)-based and titanium (Ti)-free alloy, a Cu wiring layer formed on the conductive layer, a semiconductor element mounted on the Cu wiring layer, a sealing resin sealing the semiconductor element, and an external terminal connected to the conductive layer. The conductive layer includes the exposed conductive portion exposed from the organic film by entering the through hole. The external terminal is in contact with the exposed conductive portion.

公开(公告)号：US20170287624A1

公开(公告)日：2017-10-05

申请号：US15624205

申请日：2017-06-15

Applicant: ROHM CO., LTD.

Inventor： Kosei OSADA ,  Isamu NISHIMURA ,  Tetsuya KAGAWA ,  Daiki YANAGISHIMA ,  Toshiyuki ISHIKAWA ,  Michihiko MIFUJI ,  Satoshi KAGEYAMA ,  Nobuyuki KASAHARA

IPC: H01F27/28 ,  H01L23/522 ,  H01L23/58 ,  H01L23/495 ,  H01L23/64

CPC classification number: H01F27/288 ,  H01F27/2804 ,  H01F2027/2819 ,  H01L23/3107 ,  H01L23/49575 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L23/645 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/06135 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104

Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

公开(公告)号：US20160027690A1

公开(公告)日：2016-01-28

申请号：US14876640

申请日：2015-10-06

Applicant: ROHM CO., LTD.

Inventor： Yuichi NAKAO ,  Satoshi KAGEYAMA ,  Masaru NAITOU

IPC: H01L21/768

CPC classification number: H01L23/528 ,  B23D51/125 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/05 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079

Abstract: The semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer laminated on the semiconductor substrate, a first metal wiring pattern embedded in a wire-forming region of the first insulating layer, a second insulating layer laminated on the first insulating layer, a second metal wiring pattern embedded in a wire-forming region of the second insulating layer and first dummy metal patterns embedded each in a wire-opposed region opposing to the wire-forming region of the second insulating layer and in a non-wire-opposed region opposing to a non-wire-forming region other than the wire-forming region of the second insulating layer, the wire-opposed region and the non-wire-opposed region each in a non-wire-forming region other than the wire-forming region of the first insulating layer.

公开(公告)号：US20160013143A1

公开(公告)日：2016-01-14

申请号：US14793057

申请日：2015-07-07

Applicant: ROHM CO., LTD.

Inventor： Kenji FUJII ,  Satoshi KAGEYAMA

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48451 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/78306 ,  H01L2224/85181 ,  H01L2224/85439 ,  H01L2224/85447 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention provides an electronic device that is able to achieve an improvement in yield or an electronic device that is able to prevent a sealing resin from exfoliating from a sub-electrode. The electronic device is provided with an electronic element and a wire bonded to the electronic element. The electronic element includes a bonding pad to which the wire is bonded. The bonding pad includes a Pd layer that directly contacts the wire.

Abstract translation: 本发明提供能够实现产量提高的电子设备或能够防止密封树脂从副电极剥离的电子设备。 电子装置设置有电子元件和接合到电子元件的导线。 电子元件包括接合焊盘，接合线与导线接合。 焊盘包括直接接触导线的Pd层。

公开(公告)号：US20150162396A1

公开(公告)日：2015-06-11

申请号：US14560745

申请日：2014-12-04

Applicant: ROHM CO., LTD.

Inventor： Ryoutaro YAGI ,  Satoshi KAGEYAMA

IPC: H01L49/02 ,  H01L21/308 ,  H01L27/01

CPC classification number: H01L28/20 ,  H01L21/3081 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/016 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first etching stopper film and a second etching stopper film that are formed to be spaced apart from one another on a first inter-layer insulating film; a metal thin film resistor formed to extend over the first and second etching stopper films; a second inter-layer insulating film formed on the first inter-layer insulating film to cover the first and second etching stopper films and the metal thin film resistor; a first contact hole formed in the second inter-layer insulating film to extend from a surface of the second inter-layer insulating film onto the first etching stopper film by penetrating through the metal thin film resistor; and a second contact hole formed in the second inter-layer insulating film to extend from a surface of the second inter-layer insulating film onto the second etching stopper film by penetrating through the metal thin film resistor.

Abstract translation: 半导体器件包括在第一层间绝缘膜上形成为彼此间隔开的第一蚀刻停止膜和第二蚀刻阻挡膜; 形成为在所述第一和第二蚀刻停止膜上延伸的金属薄膜电阻器; 形成在第一层间绝缘膜上以覆盖第一和第二蚀刻阻挡膜和金属薄膜电阻器的第二层间绝缘膜; 形成在第二层间绝缘膜中的第一接触孔，通过穿过金属薄膜电阻器从第二层间绝缘膜的表面延伸到第一蚀刻阻挡膜上; 以及形成在所述第二层间绝缘膜中的第二接触孔，其通过穿过所述金属薄膜电阻器从所述第二层间绝缘膜的表面延伸到所述第二蚀刻停止膜上。

公开(公告)号：US20150137314A1

公开(公告)日：2015-05-21

申请号：US14537234

申请日：2014-11-10

Applicant: ROHM CO., LTD.

Inventor： Kosei OSADA ,  Isamu NISHIMURA ,  Tetsuya KAGAWA ,  Daiki YANAGISHIMA ,  Toshiyuki ISHIKAWA ,  Michihiko MIFUJI ,  Satoshi KAGEYAMA ,  Nobuyuki KASAHARA

IPC: H01L49/02 ,  H01L23/552 ,  H01F27/28 ,  H01L23/31

CPC classification number: H01F27/288 ,  H01F27/2804 ,  H01F2027/2819 ,  H01L23/3107 ,  H01L23/49575 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L23/645 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/06135 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104

Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Abstract translation: 本发明的半导体器件包括绝缘层，高压线圈和低压线圈，其在垂直方向上以间隔设置在绝缘层中;低电位部分设置在设置在低电压区域周围的低电压区域 高压线圈的平面图的高电压区域，并且与低于高压线圈的电位相连接;以及电场屏蔽部，其设置在高电压线圈与低电压区域之间，并且具有电浮极金属部件 。

公开(公告)号：US20140299990A1

公开(公告)日：2014-10-09

申请号：US14243245

申请日：2014-04-02

Applicant: ROHM CO., LTD.

Inventor： Satoshi KAGEYAMA ,  Isamu NISHIMURA

IPC: H01L23/00

CPC classification number: H01L24/45 ,  H01L23/3121 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/0347 ,  H01L2224/0382 ,  H01L2224/03906 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2924/181 ,  H01L2924/01204 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The semiconductor device of the present invention includes an insulating layer, a copper wiring for wire connection formed on the insulating layer, a shock absorbing layer formed on an upper surface of the copper wiring, the shock absorbing layer being made of a metallic material with a hardness higher than copper, a bonding layer formed on the shock absorbing layer, the bonding layer having a connection surface for a wire, and a side protecting layer covering a side surface of the copper wiring, wherein the side protecting layer has a thickness thinner than a distance from the upper surface of the copper wiring to the connection surface of the bonding layer.

Abstract translation: 本发明的半导体器件包括绝缘层，形成在绝缘层上的用于电线连接的铜布线，形成在铜布线的上表面上的减震层，该冲击吸收层由金属材料制成，具有 形成在冲击吸收层上的接合层，具有线的连接面的接合层和覆盖铜布的侧面的侧保护层，其中侧保护层的厚度比 从铜布线的上表面到接合层的连接表面的距离。