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    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE
    11.
    发明申请
    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE 审中-公开

    公开(公告)号：US20200073756A1

    公开(公告)日：2020-03-05

    申请号：US16565848

    申请日：2019-09-10

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE ,  Brent S. HAUKNESS ,  Lawrence LAI

    IPC: G06F11/10

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE
    13.
    发明申请
    HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE 审中-公开
    具有改进的指令地址和芯片选择信号模式的高容量存储器系统

    公开(公告)号：US20160314085A1

    公开(公告)日：2016-10-27

    申请号：US15101870

    申请日：2014-12-18

    Applicant: RAMBUS INC.

    Inventor： Frederick A. WARE ,  Abhijit ABHYANKAR ,  Suresh RAJAN

    IPC: G06F13/16 ,  G06F13/42

    CPC classification number: G06F13/1673 ,  G06F13/4243

    Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

    Abstract translation: 存储器控制器和存储器模块中的缓冲器各自以两种模式运行，这取决于控制器和模块通过其连接的主板的类型。 在第一模式中，控制器独立地向每个模块发送解码的芯片选择信号，并且主板数据信道使用到每个模块的多点连接。 在第二模式中，母板具有到每个存储器模块的点对点数据信道和命令地址连接，并且控制器向每个模块发送完全编码的芯片选择信号组。 缓冲器以模态方式进行操作，以根据模式正确选择每个事务的一个或多个模块上的存储器设备的等级或部分等级。

    HIGH CAPACITY MEMORY SYSTEM
    14.
    发明申请
    HIGH CAPACITY MEMORY SYSTEM 有权
    高容量存储器系统

    公开(公告)号：US20160217839A1

    公开(公告)日：2016-07-28

    申请号：US15024454

    申请日：2014-09-24

    Applicant: RAMBUS INC.

    Inventor： Frederick A. WARE ,  Suresh RAJAN

    IPC: G11C7/10

    CPC classification number: G11C7/1063 ,  G11C5/04 ,  G11C5/063 ,  G11C7/10 ,  G11C7/1072 ,  G11C29/025 ,  G11C29/028

    Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory module includes multiple device sites coupled to the a data query (DQ) buffer component via data lines and coupled to a command and address (CA) buffer component via chip select (CS) lines. A first number of the CS lines between the CA buffer component and any combination of two or more of the multiple device sites is greater than a second number of the CS lines between the CA buffer component and a single one of the multiple device sites.

    Abstract translation: 这里描述的实施例描述了用于存储器系统的技术。 存储器模块的一个实现包括经由数据线耦合到数据查询（DQ）缓冲器组件的多个设备站点，并经由芯片选择（CS）线路耦合到命令和地址（CA）缓冲器组件。 CA缓冲器组件与多个设备站点中的两个或多个的任何组合之间的第一个CS行数大于CA缓冲器组件与多个设备站点中的单个站点之间的CS行的第二个数量。

    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE
    15.
    发明公开
    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE 审中-公开

    公开(公告)号：US20240036975A1

    公开(公告)日：2024-02-01

    申请号：US18230403

    申请日：2023-08-04

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE ,  Brent S. HAUKNESS ,  Lawrence LAI

    IPC: G06F11/10

    CPC classification number: G06F11/1076 ,  G06F11/1048

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    COMMAND/ADDRESS CHANNEL ERROR DETECTION
    16.
    发明申请
    COMMAND/ADDRESS CHANNEL ERROR DETECTION 有权

    公开(公告)号：US20210241844A1

    公开(公告)日：2021-08-05

    申请号：US17049282

    申请日：2019-03-20

    Applicant: Rambus Inc.

    Inventor： John Eric LINSTADT ,  Frederick A. WARE

    IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C8/18

    Abstract: A memory component and a controller communicate commands and data with each other The commands to activate and then access data, and the data itself, are all communicated between a controller and the memory component at different times. The controller and memory component each calculate a respective error detecting code (EDC) values on the activate command information (e.g., bank address and row address) and store them indexed by the bank address. When the memory component is accessed, retrieved EDC values are combined with EDC values calculated from the access command information, and the data itself. The memory component transmits its combined EDC value to the controller for checking.

    ADJUSTABLE ACCESS ENERGY AND ACCESS LATENCY MEMORY SYSTEM AND DEVICES
    17.
    发明申请
    ADJUSTABLE ACCESS ENERGY AND ACCESS LATENCY MEMORY SYSTEM AND DEVICES 审中-公开

    公开(公告)号：US20200012429A1

    公开(公告)日：2020-01-09

    申请号：US16518198

    申请日：2019-07-22

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE ,  John Eric LINSTADT

    IPC: G06F3/06 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/22 ,  G11C7/18 ,  G11C11/4097

    Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

    DYNAMICALLY CHANGING DATA ACCESS BANDWIDTH BY SELECTIVELY ENABLING AND DISABLING DATA LINKS
    19.
    发明申请
    DYNAMICALLY CHANGING DATA ACCESS BANDWIDTH BY SELECTIVELY ENABLING AND DISABLING DATA LINKS 审中-公开

    公开(公告)号：US20190250695A1

    公开(公告)日：2019-08-15

    申请号：US16272346

    申请日：2019-02-11

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE

    IPC: G06F1/3287 ,  G06F1/3293 ,  G06F1/3234 ,  G06F13/16

    CPC classification number: G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  G06F1/3293 ,  G06F13/1694 ,  Y02D10/151 ,  Y02D10/157

    Abstract: Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. The bandwidth is changed by selectively enabling and disabling individual control links and data links that carry the information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During one or more lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.

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