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    Formation of a channel semiconductor alloy by a nitride hard mask layer and an oxide mask
    12.
    发明授权
    Formation of a channel semiconductor alloy by a nitride hard mask layer and an oxide mask 有权
    通过氮化物硬掩模层和氧化物掩模形成沟道半导体合金

    公开(公告)号：US08673710B2

    公开(公告)日：2014-03-18

    申请号：US13197387

    申请日：2011-08-03

    Applicant: Stephan Kronholz ,  Rohit Pal

    Inventor： Stephan Kronholz ,  Rohit Pal

    IPC: H01L21/8238

    CPC classification number: H01L21/823878 ,  H01L21/823807 ,  H01L21/823814

    Abstract: When forming sophisticated high-k metal gate electrode structures, the uniformity of the device characteristics may be enhanced by growing a threshold adjusting semiconductor alloy on the basis of a hard mask regime, which may result in a less pronounced surface topography, in particular in densely packed device areas. To this end, in some illustrative embodiments, a deposited hard mask material may be used for selectively providing an oxide mask of reduced thickness and superior uniformity.

    Abstract translation: 当形成复杂的高k金属栅电极结构时，可以通过基于硬掩模方式生长阈值调节半导体合金来增强器件特性的均匀性，这可能导致不太显着的表面形貌，特别是在密集 包装设备区域。 为此，在一些说明性实施例中，沉积的硬掩模材料可用于选择性地提供厚度减小和均匀性优异的氧化物掩模。

    Method of manufacturing a transistor device having asymmetric embedded strain elements
    15.
    发明授权
    Method of manufacturing a transistor device having asymmetric embedded strain elements 有权
    制造具有非对称嵌入式应变元件的晶体管器件的方法

    公开(公告)号：US08293609B2

    公开(公告)日：2012-10-23

    申请号：US13355221

    申请日：2012-01-20

    Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

    Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

    IPC: H01L21/336

    CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

    Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

    Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

    Transistor device having asymmetric embedded strain elements and related manufacturing method
    16.
    发明授权
    Transistor device having asymmetric embedded strain elements and related manufacturing method 有权
    具有不对称嵌入式应变元件的晶体管器件及相关制造方法

    公开(公告)号：US08148750B2

    公开(公告)日：2012-04-03

    申请号：US13052969

    申请日：2011-03-21

    Applicant: Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

    Inventor： Rohit Pal ,  Frank Bin Yang ,  Michael J. Hargrove

    IPC: H01L21/02

    CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7848

    Abstract: Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

    Abstract translation: 提供半导体晶体管器件及相关制造方法。 示例性晶体管器件包括其中限定有沟道区的半导体材料层和覆盖沟道区的栅极结构。 凹槽在与沟道区相邻的半导体材料层中形成，使得凹槽朝向沟道区不对称地延伸。 晶体管器件还包括形成在凹槽中的应力诱导半导体材料。 应力诱导半导体材料的不对称轮廓以不会加剧短通道效应的方式提高载流子迁移率。

    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
    17.
    发明授权
    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods 有权
    用于在由这种方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法

    公开(公告)号：US08084828B2

    公开(公告)日：2011-12-27

    申请号：US12815129

    申请日：2010-06-14

    Applicant: Rohit Pal ,  Man Fai Ng ,  David Brown

    Inventor： Rohit Pal ,  Man Fai Ng ,  David Brown

    IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L21/28247

    Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.

    Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 在一个实施例中，一种用于制造半导体器件的方法包括：形成包括覆盖在半导体衬底上的第一栅极叠层形成层并且围绕栅堆叠的侧壁形成第一侧壁隔离物的栅叠层。 在形成第一侧壁间隔物的步骤之后，暴露第一栅叠层形成层的一部分。 使用栅极堆叠和第一侧壁间隔物作为蚀刻掩模来各向异性蚀刻暴露部分。 在各向异性蚀刻的步骤之后，第二侧壁间隔物邻近第一侧壁间隔件形成。

    SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    18.
    发明申请
    SELF-ALIGNED EMBEDDED SiGe STRUCTURE AND METHOD OF MANUFACTURING THE SAME 失效
    自对准嵌入式SiGe结构及其制造方法

    公开(公告)号：US20110298008A1

    公开(公告)日：2011-12-08

    申请号：US12795683

    申请日：2010-06-08

    Applicant: Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

    Inventor： Brian J. Greene ,  William K. Henson ,  Judson R. Holt ,  Michael D. Steigerwalt ,  Kuldeep Amarnath ,  Rohit Pal ,  Johan W. Weijtmans

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/66636 ,  H01L21/3247 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7848

    Abstract: A low energy surface is formed by a high temperature anneal of the surfaces of trenches on each side of a gate stack. The material of the semiconductor layer reflows during the high temperature anneal such that the low energy surface is a crystallographic surface that is at a non-orthogonal angle with the surface normal of the semiconductor layer. A lattice mismatched semiconductor material is selectively grown on the semiconductor layer to fill the trenches, thereby forming embedded lattice mismatched semiconductor material portions in source and drain regions of a transistor. The embedded lattice mismatched semiconductor material portions can be in-situ doped without increasing punch-through. Alternately, a combination of intrinsic selective epitaxy and ion implantation can be employed to form deep source and drain regions.

    Abstract translation: 低能量表面通过栅极堆叠的每一侧的沟槽表面的高温退火形成。 半导体层的材料在高温退火期间回流，使得低能表面是与半导体层的表面法线成非正交角的结晶表面。 在半导体层上选择性地生长晶格失配的半导体材料以填充沟槽，从而在晶体管的源极和漏极区域中形成嵌入的晶格失配的半导体材料部分。 嵌入的晶格不匹配的半导体材料部分可以原位掺杂而不增加穿通。 或者，可以采用固有选择性外延和离子注入的组合来形成深的源极和漏极区域。

    Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods
    19.
    发明授权
    Metal oxide semiconductor transistor with reduced gate height, and related fabrication methods 有权
    具有降低栅极高度的金属氧化物半导体晶体管及相关制造方法

    公开(公告)号：US07960229B2

    公开(公告)日：2011-06-14

    申请号：US12100598

    申请日：2008-04-10

    Applicant: Frank Bin Yang ,  Rohit Pal ,  Scott Luning

    Inventor： Frank Bin Yang ,  Rohit Pal ,  Scott Luning

    IPC: H01L21/336

    CPC classification number: H01L29/66628 ,  H01L29/66772 ,  H01L29/78618

    Abstract: A metal oxide semiconductor transistor device having a reduced gate height is provided. One embodiment of the device includes a substrate having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, and source/drain recesses formed in the semiconductor material adjacent to the gate structure, such that remaining semiconductor material is located below the source/drain recesses. The device also includes shallow source/drain implant regions formed in the remaining semiconductor material, and epitaxially grown, in situ doped, semiconductor material in the source/drain recesses.

    Abstract translation: 提供了具有减小的栅极高度的金属氧化物半导体晶体管器件。 器件的一个实施例包括具有半导体材料层的衬底，覆盖半导体材料层的栅极结构以及形成在与栅极结构相邻的半导体材料中的源极/漏极凹槽，使得剩余的半导体材料位于 源极/漏极凹槽。 器件还包括在剩余半导体材料中形成的浅源极/漏极注入区域，以及在源极/漏极凹槽中外延生长的原位掺杂的半导体材料。

    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods
    20.
    发明授权
    Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods 有权
    用于在由这种方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法

    公开(公告)号：US07763508B2

    公开(公告)日：2010-07-27

    申请号：US12330292

    申请日：2008-12-08

    Applicant: Rohit Pal ,  Man Fai Ng ,  David Brown

    Inventor： Rohit Pal ,  Man Fai Ng ,  David Brown

    IPC: H01L21/336 ,  H01L21/8234

    CPC classification number: H01L29/6656 ,  H01L21/28114 ,  H01L21/28247

    Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching.

    Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 在一个实施例中，一种用于制造半导体器件的方法包括：形成包括覆盖在半导体衬底上的第一栅极叠层形成层并且围绕栅堆叠的侧壁形成第一侧壁隔离物的栅叠层。 在形成第一侧壁间隔物的步骤之后，暴露第一栅叠层形成层的一部分。 使用栅极堆叠和第一侧壁间隔物作为蚀刻掩模来各向异性蚀刻暴露部分。 在各向异性蚀刻的步骤之后，第二侧壁间隔物邻近第一侧壁间隔件形成。

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