公开(公告)号：US10418548B2

公开(公告)日：2019-09-17

申请号：US16018700

申请日：2018-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinhee Han ,  Kiseok Suh ,  KyungTae Nam ,  Woojin Kim ,  Kwangil Shin ,  Minkyoung Joo ,  Gwanhyeob Koh

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: A method of fabricating a magnetic memory device includes forming an interlayered insulating layer on a substrate, forming a landing pad to pass through the interlayered insulating layer, forming a protection insulating layer on the interlayered insulating layer to cover a top surface of the landing pad, forming a bottom electrode to pass through the protection insulating layer and through the interlayered insulating layer, forming a magnetic tunnel junction layer on the protection insulating layer; and patterning the magnetic tunnel junction layer to form a magnetic tunnel junction pattern on the bottom electrode.

公开(公告)号：US10410722B2

公开(公告)日：2019-09-10

申请号：US15987207

申请日：2018-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C14/00 ,  H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  G11C13/00 ,  G11C11/00 ,  G11C5/02 ,  H01L27/108

Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.

公开(公告)号：US20190198077A1

公开(公告)日：2019-06-27

申请号：US16290102

申请日：2019-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boyoung SEO ,  Yongkyu Lee ,  Gwanhyeob Koh ,  Choong Jae Lee

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  G11C17/02

CPC classification number: G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

公开(公告)号：US12058941B2

公开(公告)日：2024-08-06

申请号：US17083943

申请日：2020-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjae Kim ,  Kuhoon Chung ,  Gwanhyeob Koh ,  Bae-Seong Kwon ,  Kyungtae Nam

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/20 ,  H10N50/01

Abstract: A magnetic memory device includes a lower contact plug on a substrate and a data storage structure on the lower contact plug. The data storage structure includes a bottom electrode, a magnetic tunnel junction pattern, and a top electrode that are sequentially stacked on the lower contact plug. The lower contact plug and the data storage structure have a first thickness and a second thickness, respectively, in a first direction perpendicular to a top surface of the substrate. The first thickness of the lower contact plug is about 2.0 to 3.6 times the second thickness of the data storage structure.

公开(公告)号：US20210351233A1

公开(公告)日：2021-11-11

申请号：US17381768

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: H01L27/22 ,  G11C11/02 ,  G11C11/56

Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.

公开(公告)号：US20210082998A1

公开(公告)日：2021-03-18

申请号：US16895602

申请日：2020-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L23/522

Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.

公开(公告)号：US10861902B2

公开(公告)日：2020-12-08

申请号：US16010447

申请日：2018-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Ilmok Park ,  Junhee Lim

IPC: H01L27/24 ,  H01L27/1157 ,  G11C11/16 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/22 ,  H01L27/11575 ,  G11C14/00 ,  G11C5/02 ,  G11C16/04

Abstract: A semiconductor device includes first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.

公开(公告)号：US10438998B2

公开(公告)日：2019-10-08

申请号：US15828937

申请日：2017-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Hongsoo Kim ,  Junhee Lim ,  Chang-Hoon Jeon

IPC: G11C5/02 ,  H01L27/24 ,  G11C11/00 ,  H01L45/00 ,  H01L27/11573 ,  G11C13/00 ,  H01L27/22 ,  G11C11/16 ,  H01L43/08 ,  H01L49/02 ,  H01L27/11582

Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.

公开(公告)号：US10373653B2

公开(公告)日：2019-08-06

申请号：US15854551

申请日：2017-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Junhee Lim ,  Hongsoo Kim ,  Chang-hoon Jeon

IPC: G11C5/06 ,  G11C16/04 ,  G11C11/16 ,  H01L25/18 ,  H01L27/22 ,  H01L27/11573 ,  H01L43/10 ,  H01L27/1157 ,  H01L27/11582

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

公开(公告)号：US20190019554A1

公开(公告)日：2019-01-17

申请号：US15987207

申请日：2018-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGWOO KIM ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: G11C14/00 ,  H01L27/108 ,  H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  G11C13/00

CPC classification number: G11C14/0045 ,  G11C5/025 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/15 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/52 ,  G11C2213/76 ,  H01L23/528 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10897 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.