公开(公告)号：US20210036413A1

公开(公告)日：2021-02-04

申请号：US16817957

申请日：2020-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghwa KIM ,  Heeseok LEE

IPC: H01Q1/38 ,  H01L23/66 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

Abstract: An antenna module includes an antenna substrate, a fan-out package and first electrical connection structures. The antenna substrate includes a pattern layer including antenna and ground patterns, and a feeding layer under the pattern layer including a feeding network that supplies power to the antenna patterns. The fan-out package is under the antenna substrate and includes a semiconductor chip driving the antenna substrate, an encapsulant encapsulating some of the semiconductor chip, a first redistribution layer on the semiconductor chip electrically connecting the semiconductor chip with the antenna substrate, and a second redistribution layer under the semiconductor chip electrically connecting the semiconductor chip with external devices. The first electrical connection structures are between and electrically connect the antenna substrate and the fan-out package. A logic layer including logic patterns electrically connecting the pattern layer with the feeding layer in the antenna substrate in the first redistribution layer in the fan-out package.

公开(公告)号：US20160172291A1

公开(公告)日：2016-06-16

申请号：US14957053

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsuk KIM ,  HyunJong MOON ,  Tai-Hyun EUM ,  Heeseok LEE ,  Keung Beum KIM ,  Yonghoon KIM ,  Yoonha JUNG ,  Seung-Yong CHA

IPC: H01L23/498 ,  H01L23/34

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49894 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package may include a package substrate with a top surface and a bottom surface opposite to the top surface, the top surface of the package substrate configured to have a semiconductor chip mounted thereon, a power block and a ground block in the package substrate, the power block configured as a power pathway penetrating the package substrate, and the ground block configured as a ground pathway penetrating the package substrate, first vias extended from the power block and the ground block, and the first vias electrically connected to the semiconductor chip, second vias extended from the power block and the ground block toward the bottom surface of the package substrate, and block vias to penetrate the power block and the ground block, the block vias electrically connected to the semiconductor chip and electrically separated from the power block and the ground block.

Abstract translation: 半导体封装可以包括具有顶表面和与顶表面相对的底表面的封装衬底，封装衬底的顶表面被配置为具有安装在其上的半导体芯片，封装衬底中的功率块和接地块， 所述功率块被配置为穿过所述封装衬底的电力通路，并且所述接地块被配置为穿过所述封装衬底的接地路径，从所述功率块和所述接地块延伸的第一通孔以及电连接到所述半导体芯片的所述第一通孔， 第二通孔从功率块和接地块延伸到封装衬底的底表面，并且阻挡通孔以穿透功率块和接地块，块通孔电连接到半导体芯片并与功率块电分离， 地块。

公开(公告)号：US20140239477A1

公开(公告)日：2014-08-28

申请号：US14272681

申请日：2014-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsuk KIM ,  Jangwoo LEE ,  Heeseok LEE ,  Kyoungsei CHOI

IPC: H01L23/06 ,  H01L23/34 ,  H01L23/552

CPC classification number: H01L23/06 ,  H01L21/563 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/552 ,  H01L23/562 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06568 ,  H01L2924/15311 ,  H01L2924/16172 ,  H01L2924/16251 ,  H01L2924/00

Abstract: A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.

Abstract translation: 一种半导体封装，包括具有芯片安装区域和周边区域的封装基板，并且包括形成在周边区域中的接地层，在芯片安装区域中的封装基板上的第一焊球，接地层上的第二焊球，至少 可以提供在芯片安装区域中堆叠在封装基板上的一个半导体芯片，以及覆盖半导体芯片并且在周边区域中与封装基板接触的封装帽。 封装帽电连接到第二焊球。 还提供了制造半导体封装的方法。

公开(公告)号：US20220068870A1

公开(公告)日：2022-03-03

申请号：US17230192

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun So PAK ,  Junghwa KIM ,  Heeseok LEE ,  Moonseob JEONG

IPC: H01L23/00 ,  H01L23/498

Abstract: A semiconductor package may include a semiconductor chip including a chip pad, a redistribution structure including a redistribution insulation layer on the semiconductor chip and first redistribution patterns on a surface of the redistribution insulation layer, a passivation layer covering the first redistribution patterns, an UBM pattern on the passivation layer and extending into an opening of the passivation layer, a second redistribution pattern on the UBM pattern, conductive pillars on the second redistribution pattern, and a package connection terminal on the conductive pillars. The opening in the passivation layer may vertically overlap a portion of each of the first redistribution patterns. The second redistribution pattern may connect some of the first redistribution patterns to each other. Some of the conductive pillars may be connected to one another through the second redistribution pattern. The first redistribution patterns may be connected to the chip pad.

公开(公告)号：US20160329285A1

公开(公告)日：2016-11-10

申请号：US15215227

申请日：2016-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonha JUNG ,  Jongkook KIM ,  Bona BAEK ,  Heeseok LEE ,  Kyoungsei CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/552

CPC classification number: H01L23/5389 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3224 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/83471 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer.

公开(公告)号：US20160133542A1

公开(公告)日：2016-05-12

申请号：US14825831

申请日：2015-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Yong CHA ,  Keung Beum KIM ,  Yonghoon KIM ,  HyunJong MOON ,  Heeseok LEE

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/16265 ,  H01L2224/1713 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041

Abstract: A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.

Abstract translation: 半导体封装包括：封装基板，包括第一区域，穿透第一区域并在封装基板的顶表面和底表面处露出的热块;封装基板上的半导体芯片;设置在封装基板和半导体芯片之间的凸块;以及 包括与热块接触的第一凸起，以及设置在封装基板的底表面上并包括与热块接触的第一端子的端子。 热块是功率路径和接地路径之一。