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    Area effective erase voltage isolation in NAND memory
    12.
    发明授权
    Area effective erase voltage isolation in NAND memory 有权

    公开(公告)号：US10885984B1

    公开(公告)日：2021-01-05

    申请号：US16668073

    申请日：2019-10-30

    Applicant: SanDisk Technologies LLC

    Inventor： Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Yuki Fujita ,  Naoki Ookuma ,  Kazuki Yamauchi ,  Masahito Takehara ,  Toru Miwa

    IPC: G11C16/04 ,  G11C16/14 ,  H01L27/11524

    Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.

    Data latch programming algorithm for multi-bit-per-cell memory devices
    16.
    发明授权
    Data latch programming algorithm for multi-bit-per-cell memory devices 有权

    公开(公告)号：US12230335B2

    公开(公告)日：2025-02-18

    申请号：US17838717

    申请日：2022-06-13

    Applicant: SanDisk Technologies LLC

    Inventor： Toru Miwa ,  Fumiaki Toyama

    IPC: G11C16/34 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

    Abstract: A multi-stage method for programming an n-bit memory cell array using a fixed number of data latches is disclosed. The fixed number of data latches may be a reduced number of data latches in sense amplifier and data latch (SADL) peripheral circuitry than is required by existing programming techniques. As such, the die area taken up by the SADL circuitry can be reduced, which in turn, reduces overall chip area. The multi-stage programming method may include utilizing a first data latch to receive and store program page data and utilizing a second data latch to store bit information indicating which cells are to be targeted for the multi-stage programming. At each program stage, a respective program loop may be performed with respect to each threshold voltage distribution generated during a prior program stage to create two new threshold voltage distributions from the prior distribution.

    Concurrent programming of multiple cells for non-volatile memory devices
    20.
    发明授权
    Concurrent programming of multiple cells for non-volatile memory devices 有权

    公开(公告)号：US11545221B2

    公开(公告)日：2023-01-03

    申请号：US17360572

    申请日：2021-06-28

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

    IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

    Abstract: Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

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