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公开(公告)号：US20190221586A1
公开(公告)日：2019-07-18
申请号：US16208656
申请日：2018-12-04
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Wataru UESUGI , Hikaru TAMURA , Atsuo ISOBE
IPC: H01L27/12 , H01L29/786 , G11C7/04 , H03K19/0185 , H01L29/04 , H01L29/78 , H01L49/02 , H03K19/00
Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
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公开(公告)号：US20170194048A1
公开(公告)日：2017-07-06
申请号：US15464395
申请日：2017-03-21
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takahiko ISHIZU , Kiyoshi KATO , Tatsuya ONUKI , Wataru UESUGI
IPC: G11C11/419 , G11C14/00 , G06F3/06
CPC classification number: G11C5/147 , G06F3/0619 , G06F3/065 , G06F3/0685 , G11C11/419 , G11C14/0054
Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.
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公开(公告)号：US20150363136A1
公开(公告)日：2015-12-17
申请号：US14731940
申请日：2015-06-05
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Wataru UESUGI , Tomoaki ATSUMI , Naoaki TSUTSUI , Hikaru TAMURA , Takahiko ISHIZU , Takuro OHMARU
CPC classification number: G06F12/00 , G11C5/00 , H01L27/0688 , H01L27/1156 , H01L27/1225 , H01L29/24 , H01L29/7782
Abstract: A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched.
Abstract translation: 提供一种包括寄存器控制器和包括寄存器的处理器的半导体器件。 寄存器包括第一电路和包括多个存储器部分的第二电路。 第一电路和多个存储器部分可以通过处理器的算术处理来存储数据。 存储数据的多个存储器部分中的哪一个取决于数据被处理的程序。 寄存器控制器响应中断信号切换程序。 寄存器控制器可以使每次该例程的多个存储器部分中的任何一个存储在第一电路中。 寄存器控制器可以在每次该例程被切换时使存储在与该程序相对应的多个存储器部分中的任何一个存储器中的数据存储在第一电路中。
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公开(公告)号：US20150061742A1
公开(公告)日：2015-03-05
申请号：US14471322
申请日：2014-08-28
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yukio Maehashi , Seiichi YONEDA , Wataru UESUGI
CPC classification number: H03K3/012 , H03K3/356 , H03K3/356104
Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.
Abstract translation: 存储电路包括第一和第二逻辑电路，其沟道形成区域包括氧化物半导体的第一和第二晶体管以及电容器。 第一和第二晶体管串联连接，电容器连接到第一和第二晶体管的连接节点。 第一晶体管用作控制第一逻辑电路的输出端子和电容器之间的连接的开关。 第二晶体管用作控制电容器和第二逻辑电路的输入端之间的连接的开关。 其相位相互反相的时钟信号被输入到第一和第二晶体管的栅极。 由于存储电路具有少量晶体管和由时钟信号控制的少量晶体管，所以存储电路是低功率电路。
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公开(公告)号：US20170337149A1
公开(公告)日：2017-11-23
申请号：US15590406
申请日：2017-05-09
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Tatsuya ONUKI , Wataru UESUGI
IPC: G06F13/40 , G06F13/10 , G06F15/80 , G11C15/04 , G06F12/02 , G06F12/0831 , G06F13/42 , G11C14/00
CPC classification number: G06F13/40 , G06F12/0246 , G06F12/0831 , G06F13/10 , G06F13/4256 , G06F15/80 , G11C5/025 , G11C7/1039 , G11C11/4091 , G11C14/0027 , G11C14/0036 , G11C14/0054 , G11C14/0072 , G11C14/0081 , G11C15/04
Abstract: A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.
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Patent Agency Ranking
公开(公告)号：US20170309325A1
公开(公告)日：2017-10-26
申请号：US15644905
申请日：2017-07-10
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Tatsuya ONUKI , Kiyoshi KATO , Wataru UESUGI , Takahiko ISHIZU
IPC: G11C11/4091 , G11C7/02 , G11C11/4094 , H01L27/108 , G11C11/4097 , G11C5/02
CPC classification number: G11C11/4091 , G11C5/025 , G11C7/02 , G11C11/4094 , G11C11/4097 , G11C2213/71 , H01L27/10808 , H01L27/1225
Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.
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公开(公告)号：US20170221899A1
公开(公告)日：2017-08-03
申请号：US15416262
申请日：2017-01-26
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Wataru UESUGI , Hikaru TAMURA
IPC: H01L27/105 , H01L29/786 , H01L27/12
CPC classification number: H01L29/7869 , H01L27/11582 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L28/00
Abstract: An object is to provide a microcontroller (MCU) system with low power consumption. The MCU system includes a CPU, a first memory cell, and a second memory cell. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. The first memory cell functions as a data memory. The second memory cell functions as a program memory. Each of the first and second transistors contains an oxide semiconductor in a channel formation region. The capacitance of the second capacitor is preferably larger than that of the first capacitor.
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公开(公告)号：US20170187360A1
公开(公告)日：2017-06-29
申请号：US15387216
申请日：2016-12-21
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Wataru UESUGI , Takeshi OSADA
CPC classification number: H03K3/356182 , G09G3/20 , G09G3/3266 , G09G3/3648 , G09G3/3696 , G09G2300/0408 , G09G2300/0426 , G09G2300/0871 , G09G2310/0267 , G09G2310/0286 , G09G2310/0289 , H01L27/1225
Abstract: A level-shift circuit that operates stably is provided. The level-shift circuit has a function of boosting a first signal having an amplitude voltage between a first voltage and a second voltage to a second signal having an amplitude voltage between a third voltage and the second voltage. The level-shift circuit includes first to eighth transistors. Gates of the third and seventh transistors are electrically connected to a wiring for transmitting a third signal for controlling the amounts of current flowing into one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, and one of a source and a drain of the sixth transistor.
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公开(公告)号：US20160373089A1
公开(公告)日：2016-12-22
申请号：US15254373
申请日：2016-09-01
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Yukio MAEHASHI , Siichi YONEDA , Wataru UESUGI
CPC classification number: H03K3/012 , H03K3/356 , H03K3/356104
Abstract: The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit.
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公开(公告)号：US20160284407A1
公开(公告)日：2016-09-29
申请号：US15081998
申请日：2016-03-28
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Tatsuya ONUKI , Wataru UESUGI
CPC classification number: G11C14/0054 , G11C5/063 , G11C5/10
Abstract: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.
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