公开(公告)号：US10033361B2

公开(公告)日：2018-07-24

申请号：US15387216

申请日：2016-12-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru Uesugi ,  Takeshi Osada

IPC: H03K3/356 ,  H01L27/12 ,  G09G3/36

CPC classification number: H03K3/356182 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/3648 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2300/0871 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0289 ,  H01L27/1207 ,  H01L27/1225

Abstract: A level-shift circuit that operates stably is provided. The level-shift circuit has a function of boosting a first signal having an amplitude voltage between a first voltage and a second voltage to a second signal having an amplitude voltage between a third voltage and the second voltage. The level-shift circuit includes first to eighth transistors. Gates of the third and seventh transistors are electrically connected to a wiring for transmitting a third signal for controlling the amounts of current flowing into one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, one of a source and a drain of the fifth transistor, and one of a source and a drain of the sixth transistor.

公开(公告)号：US09443564B2

公开(公告)日：2016-09-13

申请号：US14993375

申请日：2016-01-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko Ishizu ,  Wataru Uesugi ,  Kiyoshi Kato ,  Tatsuya Onuki

IPC: G11C5/14 ,  G11C14/00

CPC classification number: G11C11/419 ,  G06F2212/221 ,  G11C5/14 ,  G11C5/148 ,  G11C11/418 ,  G11C14/0054 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/02631 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device having a novel structure. To provide a semiconductor device excellent in reducing power consumption. A memory cell including an SRAM capable of backing up data to the nonvolatile memory and a peripheral circuit of the memory cell are configured to offer different power gating states. In a first period, which is extremely short, the bit line is brought into an electrically floating state by turning off the switch. In a second period, which is longer than the first period, power gating is performed on the memory cell. In a third period, which is longer than the second period, power gating is performed on the memory cell and the peripheral circuits.

Abstract translation: 提供具有新颖结构的半导体器件。 提供一种降低功耗的半导体器件。 包括能够将数据备份到非易失性存储器的SRAM和存储器单元的外围电路的存储单元被配置为提供不同的功率门控状态。 在非常短的第一时段中，通过关闭开关使位线进入电浮动状态。 在比第一期间长的第二期间，对存储单元进行电力门控。 在比第二时段长的第三时段中，对存储单元和外围电路进行功率门控。

公开(公告)号：US09438234B2

公开(公告)日：2016-09-06

申请号：US14944262

申请日：2015-11-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yukio Maehashi ,  Wataru Uesugi

IPC: H03K19/00 ,  H03K3/356 ,  H03K19/173 ,  H03K19/177 ,  H03K19/0185 ,  H03K3/3562 ,  G11C19/28 ,  G11C19/18 ,  G11C11/24 ,  G11C11/34

CPC classification number: H03K19/0013 ,  G11C5/141 ,  G11C5/148 ,  G11C7/222 ,  G11C11/24 ,  G11C11/34 ,  G11C14/0054 ,  G11C19/184 ,  G11C19/28 ,  H03K3/012 ,  H03K3/356008 ,  H03K3/356104 ,  H03K3/356139 ,  H03K3/356156 ,  H03K3/356173 ,  H03K3/356191 ,  H03K3/35625 ,  H03K19/01855 ,  H03K19/173 ,  H03K19/177

Abstract: A logic circuit that can retain a state even without power supply is provided. The logic circuit includes a first circuit, a pair of retention circuits, and a second circuit. The pair of retention circuits includes two switches electrically connected to each other in series and a capacitor electrically connected to a connection portion of the two switches. Each of the two switches is formed using an oxide semiconductor transistor. The first circuit has a function of generating complementary data from a piece of input data. The pair of retention circuits retains the complementary data. The second circuit has a function of amplifying the complementary data retained in the pair of retention circuits.

Abstract translation: 提供了即使没有电源也能保持状态的逻辑电路。 逻辑电路包括第一电路，一对保持电路和第二电路。 一对保持电路包括串联电连接的两个开关和电连接到两个开关的连接部分的电容器。 两个开关中的每一个都使用氧化物半导体晶体管形成。 第一电路具有从一条输入数据产生互补数据的功能。 该对保持电路保留补充数据。 第二电路具有放大保持在一对保持电路中的互补数据的功能。

公开(公告)号：US09293186B2

公开(公告)日：2016-03-22

申请号：US14208428

申请日：2014-03-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Naoaki Tsutsui ,  Atsuo Isobe ,  Wataru Uesugi ,  Takuro Ohmaru

IPC: G11C11/24 ,  G11C11/401 ,  G11C11/403

CPC classification number: G11C11/4093 ,  G11C11/24 ,  G11C11/401 ,  G11C11/403

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract translation: 存储器件包括：第一存储器电路，包括硅晶体管，包括硅晶体管的选择电路和包括氧化物半导体晶体管和存储电容器的第二存储器电路，其中存储电容器的一个端子连接到两个 氧化物半导体晶体管串联连接，第二存储电路的输出连接到选择电路的第二输入端，第二存储电路的输入端连接到选择电路的第一输入端或输出端 的第一存储器电路。

公开(公告)号：US12057451B2

公开(公告)日：2024-08-06

申请号：US17845112

申请日：2022-06-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

IPC: G11C7/06 ,  G11C7/04 ,  H01L27/12 ,  H01L29/04 ,  H01L29/78 ,  H01L29/786 ,  H01L49/02 ,  H03K19/00 ,  H03K19/0185

CPC classification number: H01L27/1207 ,  G11C7/04 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/04 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78648 ,  H01L29/78696 ,  H03K19/0008 ,  H03K19/018514

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US10825836B2

公开(公告)日：2020-11-03

申请号：US16657277

申请日：2019-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

IPC: H03K19/00 ,  H01L27/12 ,  H01L29/786 ,  H01L49/02 ,  H01L29/04 ,  H01L29/78 ,  H03K19/0185 ,  G11C7/04

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US10453863B2

公开(公告)日：2019-10-22

申请号：US16208656

申请日：2018-12-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Wataru Uesugi ,  Hikaru Tamura ,  Atsuo Isobe

IPC: H03K19/00 ,  H01L27/12 ,  H01L29/786 ,  G11C7/04 ,  H01L29/04 ,  H01L29/78 ,  H01L49/02 ,  H03K19/0185

Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.

公开(公告)号：US09704562B2

公开(公告)日：2017-07-11

申请号：US14872535

申请日：2015-10-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Wataru Uesugi ,  Takahiko Ishizu

IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  H01L27/108 ,  G11C5/02

CPC classification number: G11C11/4091 ,  G11C5/025 ,  G11C7/02 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2213/71 ,  H01L27/10808

Abstract: A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

公开(公告)号：US09640255B2

公开(公告)日：2017-05-02

申请号：US15081998

申请日：2016-03-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Wataru Uesugi

IPC: G11C5/06 ,  G11C14/00 ,  G11C5/10

CPC classification number: G11C14/0054 ,  G11C5/063 ,  G11C5/10

Abstract: To provide a semiconductor device including a volatile memory which achieves high speed operation and lower power consumption. For example, the semiconductor device includes an SRAM provided with first and second data holding portions and a non-volatile memory provided with third and fourth second data holding portions. The first data holding portion is electrically connected to the fourth data holding portion through a transistor. The second data holding portion is electrically connected to the third data holding portion through a transistor. While the SRAM holds data, the transistor is on so that both the SRAM and the non-volatile memory hold the data. Then, the transistor is turned off before supply of power is stopped, so that the data becomes non-volatile.

公开(公告)号：US09536592B2

公开(公告)日：2017-01-03

申请号：US15072432

申请日：2016-03-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Naoaki Tsutsui ,  Atsuo Isobe ,  Wataru Uesugi ,  Takuro Ohmaru

IPC: G11C11/24 ,  G11C11/4093 ,  G11C11/403 ,  G11C11/401

CPC classification number: G11C11/4093 ,  G11C11/24 ,  G11C11/401 ,  G11C11/403

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract translation: 存储器件包括：第一存储器电路，包括硅晶体管，包括硅晶体管的选择电路和包括氧化物半导体晶体管和存储电容器的第二存储器电路，其中存储电容器的一个端子连接到两个 氧化物半导体晶体管串联连接，第二存储电路的输出连接到选择电路的第二输入端，第二存储电路的输入端连接到选择电路的第一输入端或输出端 的第一存储器电路。