中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

35 records (took 0.033 seconds)

    INTEGRATED CANTILEVER SWITCH
    11.
    发明申请
    INTEGRATED CANTILEVER SWITCH 审中-公开
    集成式CANTILEVER开关

    公开(公告)号：US20160380118A1

    公开(公告)日：2016-12-29

    申请号：US15260206

    申请日：2016-09-08

    Applicant: STMICROELECTRONICS, INC.

    Inventor： Qing LIU ,  John H. ZHANG

    IPC: H01L29/84 ,  H01L21/306 ,  H01L21/02 ,  H01H49/00 ,  H01H59/00

    CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

    Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

    Abstract translation: 纳米级机电开关形式的集成晶体管消除了CMOS电流泄漏并提高了开关速度。 纳米尺度的机电开关具有从衬底的一部分延伸到空腔中的半导体悬臂。 悬臂响应于施加到晶体管栅极的电压而弯曲，从而在栅极下形成导电沟道。 当设备关闭时，悬臂返回到其静止位置。 悬臂的这种运动打破了电路，恢复了阻挡电流的门下方的空隙，从而解决了泄漏问题。 纳米机电开关的制造与现有的CMOS晶体管制造工艺兼容。 通过掺杂悬臂并使用背偏压和金属悬臂尖，可以进一步提高开关的灵敏度。 纳米机电开关的占地面积可以小至0.1×0.1μm2。

    SIZE-CONTROLLABLE OPENING AND METHOD OF MAKING SAME
    12.
    发明申请
    SIZE-CONTROLLABLE OPENING AND METHOD OF MAKING SAME 有权
    尺寸可控开放及其制作方法

    公开(公告)号：US20130093289A1

    公开(公告)日：2013-04-18

    申请号：US13645658

    申请日：2012-10-05

    Applicant: STMicroelectronics, Inc.

    Inventor： John H. ZHANG

    IPC: H01L41/09 ,  H01L41/22

    CPC classification number: H01L41/332 ,  H01L41/0973

    Abstract: A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.

    Abstract translation: 支撑结构包括内腔。 弹性膜延伸以将内腔分成第一腔室和第二腔室。 弹性膜包括在其上延伸的纳米尺寸的针孔，以将第一腔室与第二腔室相互连接。 弹性膜由第一电极膜和由压电绝缘膜隔开的第二电极膜形成。 提供电连接引线以支持向弹性膜的第一和第二电极膜施加偏置电流。 响应于所施加的偏置电流，弹性膜通过沿朝向第一和第二腔室之一的方向弯曲而变形，从而产生销孔直径的增加。

    SILICON ON INSULATOR DEVICE WITH PARTIALLY RECESSED GATE
    13.
    发明申请
    SILICON ON INSULATOR DEVICE WITH PARTIALLY RECESSED GATE 有权

    公开(公告)号：US20220328632A1

    公开(公告)日：2022-10-13

    申请号：US17852197

    申请日：2022-06-28

    Applicant: STMICROELECTRONICS, INC.

    Inventor： John H. ZHANG

    IPC: H01L29/10 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/786

    Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

    VERTICAL GATE-ALL-AROUND TFET
    14.
    发明申请
    VERTICAL GATE-ALL-AROUND TFET 审中-公开

    公开(公告)号：US20200006350A1

    公开(公告)日：2020-01-02

    申请号：US16510612

    申请日：2019-07-12

    Applicant: STMICROELECTRONICS, INC.

    Inventor： John H. ZHANG

    IPC: H01L27/108 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L31/0392 ,  H01L33/04 ,  H01L45/00 ,  B82Y10/00

    Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.

    VERTICAL TUNNELING FINFET
    16.
    发明申请
    VERTICAL TUNNELING FINFET 审中-公开

    公开(公告)号：US20180315850A1

    公开(公告)日：2018-11-01

    申请号：US16026663

    申请日：2018-07-03

    Applicant: STMicroelectronics, Inc.

    Inventor： Qing LIU ,  John H. ZHANG

    IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/165 ,  H01L29/739 ,  H01L29/267 ,  H01L21/8238 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/49

    Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

    GATE ALL AROUND VACUUM CHANNEL TRANSISTOR
    20.
    发明申请
    GATE ALL AROUND VACUUM CHANNEL TRANSISTOR 有权

    公开(公告)号：US20210273116A1

    公开(公告)日：2021-09-02

    申请号：US17322485

    申请日：2021-05-17

    Applicant: STMICROELECTRONICS, INC.

    Inventor： John H. ZHANG

    IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01J21/10

    Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

Patent Agency Ranking