公开(公告)号：US09728644B2

公开(公告)日：2017-08-08

申请号：US15093892

申请日：2016-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Suk Tak ,  Jongryeol Yoo ,  Hyun Jung Lee ,  Miseon Park ,  Bonyoung Koo ,  Sunjung Kim

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7849

Abstract: A semiconductor device includes a fin structure on a substrate and extending in a first direction, a gate electrode crossing over the fin structure, source/drain regions on the fin structure at opposite sides of the gate electrode, and a barrier layer between the fin structure and each of the source/drain regions. The fin structure includes a material having a lattice constant different from that of the substrate, the fin structure, the source/drain regions, and the barrier layer include germanium, and a germanium concentration in the barrier layer is greater than that in the fin structure and less than a maximum germanium concentration in each of the source/drain regions.

公开(公告)号：US09698244B2

公开(公告)日：2017-07-04

申请号：US15062742

申请日：2016-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Jaeyoung Park ,  Donghun Lee ,  Jeongho Yoo ,  Jieon Yoon ,  Kwan Heum Lee ,  Choeun Lee ,  Bonyoung Koo

IPC: H01L29/66 ,  H01L29/04 ,  H01L29/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/40 ,  H01L21/30

CPC classification number: H01L29/66636 ,  H01L21/3003 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/12 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device is provided as follows. A source/drain pattern is formed on a substrate. The source/drain pattern contains silicon atoms and germanium atoms. At least one germanium atom is removed from the germanium atoms of the source/drain pattern.

公开(公告)号：US09576840B2

公开(公告)日：2017-02-21

申请号：US14543820

申请日：2014-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyoung Park ,  Sungho Kang ,  Kichul Kim ,  Sunyoung Lee ,  Han Ki Lee ,  Bonyoung Koo

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/762 ,  H01L29/66 ,  H01L21/336 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0206 ,  H01L21/302 ,  H01L21/306 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/34 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device includes forming a first plurality of recessed regions in a substrate, the substrate having a protruded active region between the first plurality of recessed regions and the protruded active region having an upper surface and a sidewall, forming a device isolation film in the first plurality of recessed regions, the device isolation film exposing the upper surface and an upper portion of the sidewall of the protruded active region, and performing a first plasma treatment on the exposed surface of the protruded active region, wherein the plasma treatment is performed using a plasma gas containing at least one of an inert gas and a hydrogen gas in a temperature of less than or equal to about 700.

Abstract translation: 一种制造半导体器件的方法包括在衬底中形成第一多个凹陷区域，所述衬底在所述第一多个凹陷区域之间具有突出的有源区域和所述突出的有源区域具有上表面和侧壁，形成器件隔离 在所述第一多个凹陷区域中的膜，所述器件隔离膜暴露所述突出的有源区的所述上表面和所述侧壁的上部，并且对所述突出的有源区的所述暴露表面进行第一等离子体处理，其中所述等离子体处理 使用包含惰性气体和氢气中的至少一种的等离子体气体在小于或等于约700℃的温度下进行。

公开(公告)号：US09412731B2

公开(公告)日：2016-08-09

申请号：US14562788

申请日：2014-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhoon Kim ,  Bonyoung Koo ,  JinBum Kim ,  Chul Kim ,  Kwan Heum Lee ,  Byeongchan Lee ,  Sujin Jung

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7848

Abstract: Provided is a semiconductor device which includes a substrate including a first region and a second region different from the first region, a first active pattern provided on the substrate in the first region, a second active pattern provided on the substrate in the second region, a first gate structure crossing over the first active pattern and a second gate structure crossing over the second active pattern, first source/drain regions disposed on the first active pattern at opposite sides of the first gate structure, second source/drain regions disposed on the second active pattern at opposite sides of the second gate structure, and auxiliary spacers disposed in the first region to cover a lower portion of each of the first source/drain regions.

Abstract translation: 提供一种半导体器件，其包括：衬底，其包括第一区域和与第一区域不同的第二区域;设置在第一区域中的衬底上的第一有源图案，设置在第二区域中的衬底上的第二有源图案; 在第一有源图案上交叉的第一栅极结构和与第二有源图案交叉的第二栅极结构，在第一栅极结构的相对侧设置在第一有源图案上的第一源/漏区，设置在第二有源图案上的第二栅极结构的第二栅极结构 在第二栅极结构的相对侧的有源图案以及设置在第一区域中以覆盖每个第一源极/漏极区域的下部的辅助间隔物。

公开(公告)号：US09373703B2

公开(公告)日：2016-06-21

申请号：US14499922

申请日：2014-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinBum Kim ,  Jungho Yoo ,  Byeongchan Lee ,  Choeun Lee ,  Hyun Jung Lee ,  Seong Hoon Jeong ,  Bonyoung Koo

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.

Abstract translation: 一种制造半导体器件的方法包括形成从半导体衬底突出的有源图案，形成与有源图案交叉的伪栅极图案，在伪栅极图案的相对的第一和第二侧壁上形成栅极间隔物，将伪栅极图案去除 形成栅极区域，暴露栅极间隔件之间的有源图案的上表面和侧壁，凹陷由栅极区域暴露的有源图案的上表面，以形成通道凹槽区域，在通道凹槽区域中形成通道图案 选择性外延生长（SEG）工艺，以及顺序地形成覆盖栅极区域中的沟道图案的上表面和侧壁的栅极电介质层和栅电极。 沟道图案具有与半导体衬底不同的晶格常数。

公开(公告)号：US20130260554A1

公开(公告)日：2013-10-03

申请号：US13905375

申请日：2013-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。