公开(公告)号：US20240234557A1

公开(公告)日：2024-07-11

申请号：US18515102

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Jeeeun YANG ,  Sangwook KIM ,  Kyung-Eun BYUN ,  Eunkyu LEE

IPC: H01L29/76 ,  H01L21/02 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7606 ,  H01L21/02568 ,  H01L29/24 ,  H01L29/4236 ,  H01L29/66969

Abstract: Disclosed are a semiconductor device, a method of manufacturing the same, and an electronic element and an electronic apparatus each including the semiconductor device. The semiconductor device may include a substrate, a channel layer on the substrate, a first electrode and a second electrode on two opposite ends of the channel layer, respectively, and spaced apart from each other, a gate electrode on the channel layer and spaced apart from the first electrode and the second electrode, a gate dielectric material provided between the channel layer and the gate electrode, and a chalcogen compound layer being at least one of between the gate dielectric material and the channel layer, between the first electrode and the channel layer, and between the second electrode and the channel layer.

公开(公告)号：US20230072863A1

公开(公告)日：2023-03-09

申请号：US17939303

申请日：2022-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyu LEE ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Yeonchoo CHO

IPC: H01L27/108

Abstract: A semiconductor element may include a substrate including source and drain regions formed in the substrate apart from each other by a trench, a gate insulating layer covering a bottom surface and a sidewall of the trench, a gate electrode including lower and upper buried portions. The lower buried portion may be in the trench with the gate insulating layer therearound and fill a lower region of the trench. The upper buried portion may be on the lower buried portion with the gate insulating layer therearound and fill an upper region of the trench. The upper buried portion may include a two-dimensional material layer in the trench on an upper surface of the first conductive layer and an upper region of the sidewall of the gate insulating layer, and a second conductive layer in the upper region of the trench and surrounded by the two-dimensional material layer.

公开(公告)号：US20220316052A1

公开(公告)日：2022-10-06

申请号：US17711147

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon KIM ,  Kyung-Eun BYUN ,  Yeonchoo CHO ,  Keunwook SHIN ,  Eunkyu LEE ,  Changseok LEE ,  Hyunjae SONG ,  Hyeonjin SHIN ,  Jungsoo YOON ,  Soyoung LEE ,  Hyunseok LIM

IPC: C23C16/26 ,  H01L29/45 ,  H01L21/285 ,  C23C16/511 ,  C23C16/505 ,  C23C16/02

Abstract: Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/μm2 or higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

公开(公告)号：US20220173221A1

公开(公告)日：2022-06-02

申请号：US17398363

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin SHIN ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Hyunjae SONG ,  Keunwook SHIN ,  Eunkyu LEE ,  Changseok LEE ,  Yeonchoo CHO ,  Taejin CHOI

IPC: H01L29/45 ,  H01L27/108 ,  H01L29/15 ,  H01L29/40

Abstract: An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.

公开(公告)号：US20210372786A1

公开(公告)日：2021-12-02

申请号：US17145966

申请日：2021-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyu LEE ,  Yeonchoo CHO ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Hyunjae SONG ,  Hyeonjin SHIN

IPC: G01B15/02 ,  H01L21/66 ,  H01L21/285 ,  H01L29/45 ,  G01N23/2208

Abstract: A method of calculating a thickness of a graphene layer and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer, which is directly grown on a silicon substrate, includes measuring the thickness of the graphene layer directly grown on the silicon substrate, by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer and a signal intensity of a photoelectron beam emitted from the silicon substrate.

公开(公告)号：US20210355582A1

公开(公告)日：2021-11-18

申请号：US17318238

申请日：2021-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin SHIN ,  Sangwon KIM ,  Kyung-Eun BYUN ,  Eunkyu LEE ,  Changhyun KIM ,  Changseok LEE

IPC: C23C16/50 ,  C23C16/26 ,  C23C16/32 ,  C01B32/182 ,  C01B21/064 ,  C01B25/00

Abstract: Provided are a conductive structure and a method of controlling a work function of metal. The conductive structure includes a conductive material layer including metal and a work function control layer for controlling a work function of the conductive structure by being bonded to the conductive material layer. The work function control layer includes a two-dimensional material with a defect.

公开(公告)号：US20240014287A1

公开(公告)日：2024-01-11

申请号：US18338869

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyu LEE ,  Minsu SEOL ,  Keunwook SHIN

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H10B12/00 ,  H01L29/40

CPC classification number: H01L29/513 ,  H01L29/7827 ,  H01L29/4236 ,  H01L29/4958 ,  H01L29/517 ,  H10B12/34 ,  H01L29/401

Abstract: A semiconductor device may include a substrate including a source area and a drain area separated by a trench; a gate insulating layer in the trench; and a gate electrode. The gate electrode may include a lower buried portion and an upper buried portion in the trench. The lower buried portion may include a first conductive layer, and the upper buried portion may include a two-dimensional (2D) material layer and a second conductive layer. The second conductive layer may include a transition metal. The first conductive layer may include a transition metal identical to the transition metal included in the second conductive layer. The 2D material layer may include a chalcogen compound of a transition metal which is identical to the transition metal in the second conductive layer.

公开(公告)号：US20230343846A1

公开(公告)日：2023-10-26

申请号：US18151775

申请日：2023-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Eunkyu LEE ,  Changseok LEE ,  Changhyun KIM ,  Kyung-Eun BYUN

IPC: H01L29/45

CPC classification number: H01L29/45

Abstract: A semiconductor device may include a first semiconductor layer including a first semiconductor material; a metal layer facing the first semiconductor layer and having conductivity; a 2D material layer between the first semiconductor layer and the metal layer; and a second semiconductor layer between the first semiconductor layer and the 2D material layer. The second semiconductor layer may include a second semiconductor material different from the first semiconductor material. The second semiconductor layer and the 2D material layer may be in direct contact with each other. The second semiconductor material may include germanium.

公开(公告)号：US20230207312A1

公开(公告)日：2023-06-29

申请号：US18179565

申请日：2023-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyu LEE ,  Kyung-Eun BYUN ,  Hyunjae SONG ,  Hyeonjin SHIN ,  Changhyun KIM ,  Keunwook SHIN ,  Changseok LEE ,  Alum JUNG

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L21/02447 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/165 ,  H01L21/02499 ,  H01L21/02527 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02381

Abstract: Provided are a graphene structure and a method of forming the graphene structure. The graphene structure includes a substrate and graphene on a surface of the substrate. Here, a bonding region in which a material of the substrate and carbon of the graphene are covalently bonded is formed between the surface of the substrate and the graphene.

公开(公告)号：US20200058741A1

公开(公告)日：2020-02-20

申请号：US16662872

申请日：2019-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho LEE ,  Hyeonjin SHIN ,  Dongwook LEE ,  Seongjun PARK ,  Kiyoung LEE ,  Eunkyu LEE ,  Sanghyun JO ,  Jinseong HEO

IPC: H01L29/16 ,  H01L29/12 ,  H01L27/15 ,  H01L27/146 ,  H01L27/144 ,  H01L31/0352 ,  H01L51/00 ,  H01L51/05 ,  H01L31/101 ,  H01L31/028 ,  H01L31/09

Abstract: Provided are an optical sensor including graphene quantum dots and an image sensor including an optical sensing layer. The optical sensor may include a graphene quantum dot layer that includes a plurality of first graphene quantum dots bonded to a first functional group and a plurality of second graphene quantum dots bonded to a second functional group that is different from the first functional group. An absorption wavelength band of the optical sensor may be adjusted based on types of functional groups bonded to the respective graphene quantum dots and/or sizes of the graphene quantum dots.