公开(公告)号：US11482285B2

公开(公告)日：2022-10-25

申请号：US16936917

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-woo Kim ,  Jae-Kyu Lee ,  Ki-seok Suh ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Gwan-hyeob Koh

IPC: H01L23/528 ,  H01L43/12 ,  G11C14/00 ,  H01L45/00 ,  H01L29/08 ,  H01L27/108 ,  H01L29/423 ,  H01L43/08 ,  H01L43/02 ,  H01L27/24 ,  H01L27/22 ,  H01L27/105 ,  H01L27/02 ,  G11C7/10 ,  G11C11/00

Abstract: An integrated circuit (IC) device may include a single substrate that includes a single chip, and a plurality of memory cells spaced apart from one another on the substrate and having different structures. Manufacturing the IC device may include forming a plurality of first word lines in a first region of the substrate, and forming a plurality of second word lines in or on a second region of the substrate. Capacitors may be formed on the first word lines. Source lines may be formed on the second word lines. An insulation layer that covers the plurality of capacitors and the plurality of source lines may be formed in the first region and the second region. A variable resistance structure may be formed at a location spaced apart from an upper surface of the substrate by a first vertical distance, in the second region.

公开(公告)号：US11301319B2

公开(公告)日：2022-04-12

申请号：US16575615

申请日：2019-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-seok Suh ,  Gwan-hyeob Koh ,  Yoon-jong Song

IPC: G06F11/10 ,  G11C7/06 ,  G06F13/16 ,  G06F13/40

Abstract: A memory system includes a memory cell array including a first memory area and a second memory area, an input/output circuit including input/output lines for transmitting or receiving data bits and parity bits to or from the first and second memory areas, and an error correction circuit including a plurality of sub error correction circuits including a first sub error correction circuit for performing a first error correction operation on first data bits of the first memory area received through the input/output lines, and a second sub error correction circuit for performing a second error correction operation on second data bits of the second memory area received through the input/output lines. The first memory area has a higher bit error rate than the second memory area.

公开(公告)号：US11183538B2

公开(公告)日：2021-11-23

申请号：US16835667

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hyun Jeong ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/24 ,  H01L27/102 ,  H01L45/00 ,  G11C13/00

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

公开(公告)号：US20180350876A1

公开(公告)日：2018-12-06

申请号：US15858349

申请日：2017-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kil-ho Lee ,  Yoon-jong Song ,  Gwan-hyeob Koh

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes a substrate including a memory cell region and a logic region; a variable resistance memory device on the memory cell region; a logic device on the logic region; a first horizontal bit line extending in a horizontal direction on a surface of the substrate on the memory cell region and electrically connected to the variable resistance memory device; a second horizontal bit line extending in a horizontal direction on the surface of the substrate on the logic region and electrically connected to the logic device; and a vertical bit line electrically connected to the first horizontal bit line and the second horizontal bit line and extending perpendicular to the surface of the substrate.

公开(公告)号：US20180190718A1

公开(公告)日：2018-07-05

申请号：US15906550

申请日：2018-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-hyun Jeong ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L27/102

CPC classification number: H01L27/2481 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/1026 ,  H01L27/2427 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

公开(公告)号：USRE49478E1

公开(公告)日：2023-03-28

申请号：US17121968

申请日：2020-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-shik Kim ,  Gwan-hyeob Koh

IPC: H04N9/04 ,  H01L27/146 ,  H01L23/00 ,  H04N5/78 ,  H04N23/12 ,  H04N23/68 ,  H04N25/75 ,  H04N25/447 ,  H04N25/531 ,  H04N25/616 ,  H04N25/772 ,  H04N25/778 ,  H04N5/907

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a simplified stacked structure and improved operation characteristics includes an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure, and a lower chip below the upper chip including a logic region having logic circuits and a memory region having embedded therein magnetic random access memory (MRAM) used as image buffer memory for storing image data processed by the logic region.

公开(公告)号：US11201192B2

公开(公告)日：2021-12-14

申请号：US17030425

申请日：2020-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hyun Jeong ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/24 ,  H01L27/102 ,  H01L45/00 ,  G11C13/00

Abstract: A memory device includes a first electrode line layer including a plurality of first electrode lines extending on a substrate in a first direction and being spaced apart from each other, a second electrode line layer including a plurality of second electrode lines extending on the first electrode line layer in a second direction that is different from the first direction and being spaced apart from each other, and a memory cell layer including a plurality of first memory cells located at a plurality of intersections between the plurality of first electrode lines and the plurality of second electrode lines, each first memory cell including a selection device layer, an intermediate electrode and a variable resistance layer that are sequentially stacked. A side surface of the variable resistance layer is perpendicular to a top surface of the substrate or inclined to be gradually wider toward an upper portion of the variable resistance layer. The first memory cell has a side surface slope so as to have a width gradually decreasing toward its upper portion.

公开(公告)号：US20190252463A1

公开(公告)日：2019-08-15

申请号：US16392969

申请日：2019-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kil-ho Lee ,  Yoon-jong Song ,  Gwan-hyeob Koh

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1655 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes a substrate including a memory cell region and a logic region; a variable resistance memory device on the memory cell region; a logic device on the logic region; a first horizontal bit line extending in a horizontal direction on a surface of the substrate on the memory cell region and electrically connected to the variable resistance memory device; a second horizontal bit line extending in a horizontal direction on the surface of the substrate on the logic region and electrically connected to the logic device; and a vertical bit line electrically connected to the first horizontal bit line and the second horizontal bit line and extending perpendicular to the surface of the substrate.

公开(公告)号：US10319784B2

公开(公告)日：2019-06-11

申请号：US15858349

申请日：2017-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kil-ho Lee ,  Yoon-jong Song ,  Gwan-hyeob Koh

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12

Abstract: A semiconductor device includes a substrate including a memory cell region and a logic region; a variable resistance memory device on the memory cell region; a logic device on the logic region; a first horizontal bit line extending in a horizontal direction on a surface of the substrate on the memory cell region and electrically connected to the variable resistance memory device; a second horizontal bit line extending in a horizontal direction on the surface of the substrate on the logic region and electrically connected to the logic device; and a vertical bit line electrically connected to the first horizontal bit line and the second horizontal bit line and extending perpendicular to the surface of the substrate.

公开(公告)号：US10157951B2

公开(公告)日：2018-12-18

申请号：US15676069

申请日：2017-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-shik Kim ,  Gwan-hyeob Koh

IPC: H04N9/04 ,  H01L27/146 ,  H01L23/00 ,  H04N5/378 ,  H04N5/78 ,  H04N5/353 ,  H04N5/3745 ,  H04N9/07 ,  H04N5/907

Abstract: A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) with a simplified stacked structure and improved operation characteristics includes an upper chip, in which a plurality of pixels are arranged in a two-dimensional array structure, and a lower chip below the upper chip including a logic region having logic circuits and a memory region having embedded therein magnetic random access memory (MRAM) used as image buffer memory for storing image data processed by the logic region.