公开(公告)号：US09412842B2

公开(公告)日：2016-08-09

申请号：US13934369

申请日：2013-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jin-Bum Kim ,  Kyung-Bum Koo ,  Taek-Soo Jeon ,  Tae-Ho Cha ,  Judson R Holt ,  Henry K Utomo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/66636 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

Abstract: A gate pattern is formed on a first region of a substrate. An epitaxial layer is formed on a second region of the substrate. A recess is formed in the second region of the substrate by etching the epitaxial layer and the substrate underneath. The first region is adjacent to the second region.

Abstract translation: 在衬底的第一区域上形成栅极图案。 在衬底的第二区域上形成外延层。 通过在其下方蚀刻外延层和衬底，在衬底的第二区域中形成凹部。 第一区域与第二区域相邻。

公开(公告)号：US08912063B2

公开(公告)日：2014-12-16

申请号：US13829761

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Ha-Kyu Seong

IPC: H01L21/336 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a gate pattern which intersects a fin-type active pattern protruding upward from a device isolation layer. A first blocking pattern is formed on a portion of the fin-type active pattern, which does not overlap the gate pattern. Side surfaces of the portion of the fin-type active pattern are exposed. A semiconductor pattern is formed on the exposed side surfaces of the portion of the fin-type active pattern after the forming of the first blocking pattern.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括形成与从器件隔离层向上突出的翅片型有源图案相交的栅极图案。 第一阻挡图案形成在翅片型有源图案的不与栅极图案重叠的部分上。 翅片型有源图案部分的侧面露出。 在形成第一阻挡图案之后，在鳍型有源图案的部分的露出侧表面上形成半导体图案。

公开(公告)号：US20140346608A1

公开(公告)日：2014-11-27

申请号：US13901653

申请日：2013-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Bum Kim

IPC: H01L21/283 ,  H01L27/092 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/78 ,  H01L21/28008 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is provided. A plurality of first gate electrode structure is formed on a substrate. A recess is formed in the substrate, wherein the recess is formed between two adjacent first gate electrode structures of the plurality of first gate electrode structure. A diffusion prevention layer includes a first material and is formed on the recess of the substrate. A first pre-silicide layer includes a second material different from the first material and is formed on the diffusion prevention layer. A metal layer is formed on the first pre-silicide layer. The first pre-silicide layer and the metal layer are changed to a first silicide layer by performing an annealing process to the substrate. The diffusion prevention layer prevents metal atoms of the metal layer from diffusing to the substrate, and the first silicide layer comprises a monocrystalline layer.

Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成多个第一栅电极结构。 在衬底中形成凹部，其中凹部形成在多个第一栅电极结构的两个相邻的第一栅电极结构之间。 扩散防止层包括第一材料并且形成在基板的凹部上。 第一预硅化物层包括与第一材料不同的第二材料，并形成在扩散防止层上。 在第一预硅化物层上形成金属层。 通过对衬底进行退火处理，将第一预硅化物层和金属层改变为第一硅化物层。 扩散防止层防止金属层的金属原子扩散到基板，并且第一硅化物层包括单晶层。

公开(公告)号：US10297601B2

公开(公告)日：2019-05-21

申请号：US15351739

申请日：2016-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Myung-Gil Kang ,  Kang-Hun Moon ,  Cho-Eun Lee ,  Su-Jin Jung ,  Min-Hee Choi ,  Yang Xu ,  Dong-Suk Shin ,  Kwan-Heum Lee ,  Hoi-Sung Chung

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161 ,  H01L29/45 ,  H01L23/485 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US09735158B2

公开(公告)日：2017-08-15

申请号：US15177421

申请日：2016-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon Kim ,  Jin-Bum Kim ,  Kwan-Heum Lee ,  Byeong-Chan Lee ,  Cho-Eun Lee ,  Jin-Hee Han ,  Bon-Young Koo

IPC: H01L27/108 ,  H01L27/088 ,  H01L27/02 ,  H01L29/78 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

公开(公告)号：US09608117B2

公开(公告)日：2017-03-28

申请号：US15049859

申请日：2016-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Nam Kyu Kim ,  Hyun-Ho Noh ,  Dong-Chan Suh ,  Byeong-Chan Lee ,  Su-Jin Jung ,  Jin-Yeong Joe ,  Bon-Young Koo

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7856

Abstract: A semiconductor device includes an active fin structure extending in a first direction, the active fin structure including protruding portions divided by a recess, a plurality of gate structures extending in a second direction crossing the first direction and covering the protruding portions of the active fin structure, a first epitaxial pattern in a lower portion of the recess between the gate structures, a second epitaxial pattern on a portion of the first epitaxial pattern, the second epitaxial pattern contacting a sidewall of the recess, and a third epitaxial pattern on the first and second epitaxial patterns, the third epitaxial pattern filling the recess. The first epitaxial pattern includes a first impurity region having a first doping concentration, the second epitaxial pattern includes a second impurity region having a second doping concentration lower than the a first doping concentration, and the third epitaxial pattern includes a third impurity region having a third doping concentration higher than the second doping concentration. The semiconductor device may have good electrical characteristics.

公开(公告)号：US09324623B1

公开(公告)日：2016-04-26

申请号：US14554133

申请日：2014-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Bum Kim ,  Ha-Kyu Seong

IPC: H01L21/336 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/324

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/1104

Abstract: Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor includes preparing a substrate on which a first region and a second region are defined, forming a first active fin and a second active fin in the first and second regions, respectively, forming a first gate structure and a second gate structure on the substrate in a direction that crosses the first and second active fins, forming a first recess in the first active fin that is adjacent to one side surface of the first gate structure, forming a first epitaxial layer in the first recess, forming a first silicide layer on the first epitaxial layer, forming a second recess in the second active fin that is adjacent to one side surface of the second gate structure, and forming a second silicide layer in the second recess, wherein the second silicide layer includes nickel (Ni) and platinum (Pt).

Abstract translation: 提供一种制造半导体器件的方法。 制造半导体的方法包括制备其上限定了第一区域和第二区域的基板，分别在第一和第二区域中形成第一有源鳍片和第二有源鳍片，形成第一栅极结构和第二栅极 在与第一和第二活性鳍片交叉的方向上在衬底上形成结构，在第一有源鳍片中形成与第一栅极结构的一个侧表面相邻的第一凹槽，在第一凹槽中形成第一外延层， 在所述第一外延层上形成第一硅化物层，在所述第二有源鳍中形成与所述第二栅极结构的一个侧表面相邻的第二凹槽，以及在所述第二凹槽中形成第二硅化物层，其中所述第二硅化物层包括镍 Ni）和铂（Pt）。

公开(公告)号：US09087900B1

公开(公告)日：2015-07-21

申请号：US14149153

申请日：2014-01-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Bum Kim

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device is provided. At least two active fins protrude from a substrate. A gate pattern crosses the at least two active fins, covering part of each active fin. A seed layer is disposed on other part of the each active fin. The other part of the each active fin is not covered with the gate pattern. An epitaxial layer is disposed on the seed layer.

Abstract translation: 提供半导体器件。 至少两个活性翅片从基底突出。 栅极图案穿过至少两个活动鳍片，覆盖每个活动鳍片的一部分。 种子层设置在每个活性鳍片的另一部分上。 每个活动鳍片的另一部分不被栅极图案覆盖。 外延层设置在种子层上。

公开(公告)号：US09040394B2

公开(公告)日：2015-05-26

申请号：US13795701

申请日：2013-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Bum Kim

IPC: H01L21/00 ,  H01L29/16 ,  H01L21/8234

CPC classification number: H01L29/16 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a top portion and a bottom portion on a substrate, forming a sacrificial layer contacting the bottom portions of the gate patterns, forming a first spacer on lateral surfaces of the top portions of the gate patterns after forming the sacrificial layer, removing the sacrificial layer after forming the first spacer, and forming a plurality of first recesses on lateral surfaces of the gate patterns after removing the sacrificial layer.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成包括顶部和底部的多个栅极图案，形成与栅极图案的底部接触的牺牲层，在顶部的侧表面上形成第一间隔物 在形成牺牲层之后的栅极图案，在形成第一间隔物之后去除牺牲层，以及在去除牺牲层之后在栅极图案的侧表面上形成多个第一凹槽。

公开(公告)号：US20130171818A1

公开(公告)日：2013-07-04

申请号：US13728622

申请日：2012-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum Kim ,  Young-Pil Kim ,  Kwan-Heum Lee ,  Sun-Ghil Lee

IPC: H01L21/285

CPC classification number: H01L21/285 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76889 ,  H01L27/10855 ,  H01L28/91

Abstract: In a method of forming an ohmic layer of a DRAM device, the metal silicide layer between the storage node contact plug and the lower electrode of a capacitor is formed as the ohmic layer by a first heat treatment under a first temperature and an instantaneous second heat treatment under a second temperature higher than the first temperature. Thus, the metal silicide layer has a thermo-stable crystal structure and little or no agglomeration occurs on the metal silicide layer in the high temperature process. Accordingly, the sheet resistance of the ohmic layer may not increase in spite of the subsequent high temperature process.

Abstract translation: 在形成DRAM器件的欧姆层的方法中，通过在第一温度和瞬时第二次加热下的第一次热处理将存储节点接触插塞和电容器的下部电极之间的金属硅化物层形成为欧姆层 在比第一温度高的第二温度下进行处理。 因此，金属硅化物层具有热稳定的晶体结构，并且在高温工艺中在金属硅化物层上几乎或不发生聚集。 因此，尽管随后的高温处理，欧姆层的薄层电阻也可能不增加。