公开(公告)号：US20200227130A1

公开(公告)日：2020-07-16

申请号：US16574808

申请日：2019-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Heung Kim ,  Kyo-Min Sohn ,  Young-Soo Sohn

IPC: G11C29/38 ,  H01L25/065 ,  G11C11/4076 ,  G11C29/12

Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

公开(公告)号：US09589674B2

公开(公告)日：2017-03-07

申请号：US14305095

申请日：2014-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Young-Soo Sohn ,  Uk-Song Kang ,  Chul-Woo Park ,  Jung-Hwan Choi ,  Won-Il Bae ,  Kyo-Min Sohn

IPC: G11C29/00 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411

Abstract: In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

Abstract translation: 在操作存储器件的方法中，接收来自存储器控制器的命令和第一地址。 从存储器件的存储单元阵列读取包括对应于第一地址的第一组数据，对应于第二地址的第二组数据和读取奇偶校验数据的读码字。 通过使用基于读取的线字的ECC电路的操作错误检查和校正（ECC）来生成校正的数据。

公开(公告)号：US09287009B2

公开(公告)日：2016-03-15

申请号：US14595500

申请日：2015-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Chang Kang ,  Gil-Su Kim ,  Je-Min Ryu ,  Yun-Young Lee ,  Kyo-Min Sohn

IPC: G11C17/16 ,  G11C29/00 ,  G11C17/18

CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/78 ,  G11C2029/4402

Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

Abstract translation: 修复电路包括第一和第二熔丝电路，确定电路和输出电路。 第一熔丝电路包括第一熔丝，并且被配置为产生指示第一熔丝是否已被编程的第一主信号。 第二熔丝电路包括第二保险丝，并且被配置为产生指示每个第二保险丝是否被编程的第一地址。 确定电路被配置为基于第一主信号和第一地址产生检测信号。 检测信号指示是否对第二熔丝电路执行了负编程操作。 输出电路被配置为基于第一主信号和检测信号产生第二主信号，并且基于第一地址和检测信号产生对应于有缺陷的输入地址的修复地址。

公开(公告)号：US11049584B2

公开(公告)日：2021-06-29

申请号：US16574808

申请日：2019-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Heung Kim ,  Kyo-Min Sohn ,  Young-Soo Sohn

IPC: G11C29/38 ,  H01L25/065 ,  G11C29/12 ,  G11C11/4076 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/56 ,  G11C29/02 ,  G11C29/50

Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.

公开(公告)号：US09858981B2

公开(公告)日：2018-01-02

申请号：US15372750

申请日：2016-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Young Lee ,  Kyo-Min Sohn ,  Sang-Joon Hwang ,  Sung-Min Seo ,  Sang-Bo Lee ,  Nak-Won Heo

IPC: G11C17/00 ,  G11C11/406 ,  G11C17/16 ,  G11C11/408 ,  G11C29/44

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/408 ,  G11C17/16 ,  G11C29/44 ,  G11C29/783 ,  G11C29/785 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

公开(公告)号：US09831003B2

公开(公告)日：2017-11-28

申请号：US15498855

申请日：2017-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/56 ,  G11B20/18 ,  G01R31/3187 ,  G06F11/27 ,  G11C29/36 ,  G11C29/42 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4078 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

CPC classification number: G11C29/4401 ,  G01R31/3187 ,  G06F11/2053 ,  G06F11/27 ,  G11B20/1816 ,  G11C5/04 ,  G11C8/06 ,  G11C8/10 ,  G11C11/40 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56 ,  G11C29/56008 ,  G11C29/78 ,  G11C29/785 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

公开(公告)号：US09659669B2

公开(公告)日：2017-05-23

申请号：US14698219

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/56 ,  G11B20/18 ,  G01R31/3187 ,  G06F11/27 ,  G06F11/20 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/00 ,  G11C8/06 ,  G11C8/10

CPC classification number: G11C29/4401 ,  G01R31/3187 ,  G06F11/2053 ,  G06F11/27 ,  G11B20/1816 ,  G11C5/04 ,  G11C8/06 ,  G11C8/10 ,  G11C11/40 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56 ,  G11C29/56008 ,  G11C29/78 ,  G11C29/785 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.