公开(公告)号：US20170069785A1

公开(公告)日：2017-03-09

申请号：US15183869

申请日：2016-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Jo TAK ,  Sam Mook KANG ,  Mi Hyun KIM ,  Jun Youn KIM ,  Young Soo PARK ,  Misaichi TAKEUCHI

IPC: H01L33/00 ,  H01L21/02 ,  H01L21/78 ,  H01L21/683 ,  H01L21/306

CPC classification number: H01L33/0075 ,  H01L21/02005 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/7806 ,  H01L33/0066 ,  H01L33/0079

Abstract: A method of manufacturing a semiconductor substrate may include forming a first semiconductor layer on a growth substrate, forming a second semiconductor layer on the first semiconductor layer, forming a plurality of voids in the first semiconductor layer by removing portions of the first semiconductor layer that are exposed by a plurality of trenches in the second semiconductor layer, forming a third semiconductor layer on the second semiconductor layer and covering the plurality of trenches, and separating the second and third semiconductor layers from the growth substrate. on the first semiconductor layer. The third semiconductor layer are grown from the second semiconductor layer and extend above the second semiconductor layer.

Abstract translation: 制造半导体衬底的方法可以包括在生长衬底上形成第一半导体层，在第一半导体层上形成第二半导体层，在第一半导体层中形成多个空隙，通过去除第一半导体层的部分 在所述第二半导体层中由多个沟槽暴露，在所述第二半导体层上形成第三半导体层并覆盖所述多个沟槽，以及从所述生长衬底分离所述第二和第三半导体层。 在第一半导体层上。 第三半导体层从第二半导体层生长并在第二半导体层上方延伸。

公开(公告)号：US20160190388A1

公开(公告)日：2016-06-30

申请号：US15063150

申请日：2016-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIN SUB LEE ,  Jung Sub KIM ,  Sam Mook KANG ,  Yeon Woo SEO ,  Han Kyu SEONG ,  Dae Myung CHUN ,  Young Jin CHOI ,  Jae Hyeok HEO

IPC: H01L33/14 ,  H01L33/24 ,  H01L33/02 ,  H01L33/52 ,  H01L33/08 ,  H01L33/42 ,  H01L33/48 ,  H01L33/18 ,  H01L33/00

CPC classification number: H01L33/145 ,  H01L33/002 ,  H01L33/025 ,  H01L33/08 ,  H01L33/18 ,  H01L33/24 ,  H01L33/42 ,  H01L33/486 ,  H01L33/52 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: There is provided a semiconductor light emitting device including a first conductivity-type semiconductor base layer and a plurality of light emitting nanostructures disposed to be spaced apart from one another on the first conductivity-type semiconductor base layer, each light emitting nanostructure including a first conductivity-type semiconductor core, an active layer, an electric charge blocking layer, and a second conductivity-type semiconductor layer, respectively, wherein the first conductivity-type semiconductor core has different first and second crystal planes in crystallographic directions.

公开(公告)号：US20150236202A1

公开(公告)日：2015-08-20

申请号：US14516470

申请日：2014-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae Myung CHUN ,  Jung Sub KIM ,  Jin Sub LEE ,  Sam Mook KANG ,  Yeon Woo SEO ,  Han Kyu SEONG ,  Young Jin Choi ,  Jae Hyeok HEO

IPC: H01L33/24 ,  H01L33/62 ,  H01L33/08

CPC classification number: H01L33/24 ,  H01L33/0079 ,  H01L33/08 ,  H01L33/145 ,  H01L33/38 ,  H01L33/62 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A nanostructure semiconductor light emitting device may include a first conductivity-type semiconductor base layer, a mask layer disposed on the base layer and having a plurality of openings exposing portions of the base layer, a plurality of light emitting nanostructures disposed in the plurality of openings, and a polycrystalline current suppressing layer disposed on the mask layer. At least a portion of the polycrystalline current suppressing layer is disposed below the second conductivity-type semiconductor layer. Each light emitting nanostructure includes a first conductivity-type semiconductor nanocore, an active layer, and a second conductivity-type semiconductor layer.

Abstract translation: 纳米结构半导体发光器件可以包括第一导电型半导体基底层，掩模层，设置在基底层上并具有暴露基底部分的多个开口，多个发光纳米结构设置在多个开口中 以及设置在掩模层上的多晶硅电流抑制层。 多晶硅电流抑制层的至少一部分设置在第二导电型半导体层的下方。 每个发光纳米结构包括第一导电型半导体纳米孔，有源层和第二导电型半导体层。