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    Semiconductor package
    11.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11145626B2

    公开(公告)日：2021-10-12

    申请号：US16589541

    申请日：2019-10-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Hwan Hwang ,  Ji Hoon Kim ,  Ji Seok Hong ,  Tae Hun Kim ,  Hyuek Jae Lee

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

    Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.

    Three-dimensional semiconductor memory device
    12.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US10978480B2

    公开(公告)日：2021-04-13

    申请号：US16856663

    申请日：2020-04-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Byoung-Taek Kim ,  Tae Hun Kim ,  Dongkyun Seo ,  Junhee Lim

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/51 ,  H01L29/423 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

    Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

    Cooking device
    13.
    发明授权
    Cooking device 有权

    公开(公告)号：US10701770B2

    公开(公告)日：2020-06-30

    申请号：US15577297

    申请日：2016-05-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeong Jin Jang ,  Tae Hun Kim ,  In Ki Jeon ,  Kun Woo Choi ,  Yu Jeub Ha

    IPC: H05B6/76 ,  H05B6/64 ,  F24C15/04

    Abstract: A cooking appliance with an improved structure to increase visibility to get a better look at the inside of a cooking room during cooking while blocking electromagnetic waves generated in the cooking room from leaking out. The cooking appliance includes a main body configured to have having a cooking room and a door arranged on the front of the main body to open or and close the cooking room. The door includes a door frame configured to have an opening formed to see into the cooking room and a conductive border portion around the opening; a shielding member arranged to cover the opening and having a conductive blocking layer configured to block electromagnetic waves; and a fixing member arranged to combine the door frame and the shielding member.

    SEMICONDUCTOR LIGHT EMITTING DEVICE INCLUDING FLOATING CONDUCTIVE PATTERN
    14.
    发明申请
    SEMICONDUCTOR LIGHT EMITTING DEVICE INCLUDING FLOATING CONDUCTIVE PATTERN 审中-公开

    公开(公告)号：US20180198022A1

    公开(公告)日：2018-07-12

    申请号：US15725438

    申请日：2017-10-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young Kyu Sung ,  Jae Yoon Kim ,  Tae Hun Kim ,  Gam Han Yong ,  Dong Yeoul Lee ,  Su Yeol Lee

    IPC: H01L33/08 ,  H01L33/38 ,  H01L33/20

    CPC classification number: H01L33/08 ,  H01L25/0753 ,  H01L33/20 ,  H01L33/382 ,  H01L33/46

    Abstract: A semiconductor light emitting device including a floating conductive pattern is provided. The semiconductor light emitting device includes a first semiconductor layer including a recessed region and a protruding region, an active layer and a second semiconductor layer disposed on the protruding region, a contact structure disposed on the second semiconductor layer, a lower insulating pattern covering the first semiconductor layer and the contact structure, and having first and second openings, a first conductive pattern disposed on the lower insulating pattern and extending into the first opening, a second conductive pattern disposed on the lower insulating pattern and extending into the second opening, and a floating conductive pattern disposed on the lower insulating pattern. The first and second conductive patterns and the floating conductive pattern have the same thickness on the same plane.

    Method of manufacturing semiconductor light emitting device
    16.
    发明授权
    Method of manufacturing semiconductor light emitting device 有权
    制造半导体发光器件的方法

    公开(公告)号：US09466765B1

    公开(公告)日：2016-10-11

    申请号：US15056124

    申请日：2016-02-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ju Heon Yoon ,  Yeon Ji Kim ,  Yong Seok Kim ,  Tae Kang Kim ,  Tae Hun Kim

    IPC: H01L33/62 ,  H01L33/36 ,  H01L33/44 ,  H01L21/02 ,  H01L33/22 ,  H01L33/40 ,  H01L33/00

    CPC classification number: H01L33/22 ,  H01L21/02068 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/0095 ,  H01L33/20 ,  H01L33/38 ,  H01L33/40 ,  H01L33/44 ,  H01L33/62 ,  H01L2933/0016 ,  H01L2933/0025 ,  H01L2933/0066 ,  H01L2933/0091

    Abstract: A method of manufacturing a semiconductor light emitting device includes stacking a light emitting structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on a substrate; forming a first electrode and a second electrode on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively; forming an insulating layer covering the first and second electrodes and having first and second openings partially exposing surfaces of the first and second electrodes, respectively; and performing a plasma treatment on a surface of the insulating layer and the partially exposed surfaces of the first and second electrodes to form an unevenness portion on the surface of the insulating layer and form an oxygen-depleted layer on the partially exposed surfaces of the first and second electrodes.

    Abstract translation: 一种制造半导体发光器件的方法包括在衬底上堆叠包括第一导电类型半导体层，有源层和第二导电类型半导体层的发光结构; 在第一导电类型半导体层和第二导电类型半导体层上分别形成第一电极和第二电极; 形成覆盖所述第一和第二电极并且分别具有部分地暴露所述第一和第二电极的表面的第一和第二开口的绝缘层; 以及在所述绝缘层的表面和所述第一和第二电极的部分露出的表面上进行等离子体处理，以在所述绝缘层的表面上形成凹凸部，并在所述第一和第二电极的所述部分露出的表面上形成氧耗尽层 和第二电极。

    Semiconductor package
    18.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11545458B2

    公开(公告)日：2023-01-03

    申请号：US17221304

    申请日：2021-04-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sun Chul Kim ,  Tae Hun Kim ,  Ji Hwan Hwang

    IPC: H01L23/00 ,  H01L25/18 ,  H01L23/48 ,  H01L21/00

    Abstract: A semiconductor package includes a first semiconductor chip including a first body portion, a first bonding layer including a first bonding insulating layer, a first redistribution portion including first redistribution layers, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer including a second bonding insulating layer, a second redistribution portion including second redistribution layers, a second wiring insulating layer disposed between the second redistribution layers, and a second semiconductor chip disposed on the second redistribution portion. A lower surface of the first bonding insulating layer is bonded to an upper surface of the second bonding insulating layer, an upper surface of the first bonding insulating layer contacts the first body portion, a lower surface of the second bonding insulating layer contacts the second wiring insulating layer, and the first redistribution portion width is greater than the first semiconductor chip width.

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