公开(公告)号：US20170330767A1

公开(公告)日：2017-11-16

申请号：US15586716

申请日：2017-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Un-Byoung Kang ,  Tae-Je CHO ,  Hyuek-Jae Lee ,  Cha-Jea Jo

IPC: H01L21/48 ,  C23C14/58 ,  C23C14/34 ,  C23C14/20 ,  C23C14/06 ,  C23C14/04 ,  C23C14/02 ,  B05D7/00 ,  B05D3/02 ,  B05D1/38 ,  B05D1/32 ,  B05D1/00

CPC classification number: H01L21/4857 ,  B05D1/005 ,  B05D1/32 ,  B05D1/38 ,  B05D3/0209 ,  B05D7/546 ,  C23C14/024 ,  C23C14/046 ,  C23C14/0641 ,  C23C14/205 ,  C23C14/34 ,  C23C14/588 ,  C23C18/00 ,  C23C18/38 ,  H01L21/486 ,  H01L23/4334 ,  H01L23/473 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/03 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/18161 ,  H05K3/465 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/0588 ,  H01L2924/01047 ,  H01L2224/81

Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

公开(公告)号：US20160148909A1

公开(公告)日：2016-05-26

申请号：US15010438

申请日：2016-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo CHUNG ,  Jongyeon KIM ,  In-Young LEE ,  Tae-Je CHO

IPC: H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/02016 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.

公开(公告)号：US20150048493A1

公开(公告)日：2015-02-19

申请号：US14318643

申请日：2014-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hong MIN ,  Young-Kun JEE ,  Tae-Je CHO

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/373

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/433 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/95 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/2732 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83907 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2224/92225 ,  H01L2224/95 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/07802

Abstract: In one embodiment, a semiconductor package includes a circuit substrate, a plurality of semiconductor chips stacked on the circuit substrate, insulating adhesive patterns interposed between the semiconductor chips, a heat slug provided on an uppermost semiconductor chip and adhered to the uppermost semiconductor chip by a heat dissipative adhesive pattern, and a mold structure provided on the circuit substrate to cover sidewalls of the semiconductor chips, the insulating adhesive patterns, the heat dissipative adhesive pattern and the heat slug. A failure of the semiconductor package during a manufacturing process of the mold structure may be reduced. The semiconductor package may therefore have good operating characteristics and reliability.

Abstract translation: 在一个实施例中，半导体封装包括电路基板，堆叠在电路基板上的多个半导体芯片，插入在半导体芯片之间的绝缘粘合剂图案，设置在最上半导体芯片上的散热片，并通过 散热粘合剂图案，以及设置在电路基板上以覆盖半导体芯片的侧壁，绝缘粘合剂图案，散热粘合剂图案和热块的模具结构。 在模具结构的制造过程中半导体封装的故障可能会降低。 因此，半导体封装可具有良好的工作特性和可靠性。

公开(公告)号：US20150001685A1

公开(公告)日：2015-01-01

申请号：US14264123

申请日：2014-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Hyunsoo CHUNG ,  Jongyeon KIM ,  In-Young LEE ,  Tae-Je CHO

IPC: H01L21/48 ,  H01L21/02 ,  H01L23/538 ,  H01L25/00 ,  H01L25/07

CPC classification number: H01L25/0657 ,  H01L21/02016 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.

Abstract translation: 提供了具有通孔的半导体封装及其制造方法。 该方法可以包括形成包括层叠在第二半导体芯片上的第一半导体芯片的晶片级封装，形成芯片级封装，芯片级封装包括堆叠在堆叠多个芯片级封装上的第三半导体芯片上的第四半导体芯片 晶片级封装的第二半导体衬底的后表面，抛光晶片级封装的第一模具层和第一半导体芯片，以暴露第一半导体芯片的第一贯穿电极，并在第一半导体芯片上形成外部电极 半导体芯片分别连接到第一贯通电极。