公开(公告)号：US20240079323A1

公开(公告)日：2024-03-07

申请号：US18350999

申请日：2023-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung Kwon ,  Dawoon Jeong ,  Jiyoung Kim ,  Sukkang Sung ,  Woosung Yang

IPC: H01L23/528 ,  G11C5/06 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H01L23/5283 ,  G11C5/063 ,  H01L25/0655 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device includes a first conductive plate structure and a second conductive plate structure, arranged at a same vertical level on a semiconductor chip and horizontally spaced apart from each other on the semiconductor chip, a first structure on the first conductive plate structure and including first separation structures and first memory blocks, and a second structure on the second conductive plate structure and including second separation structures and second memory blocks. The first memory blocks are spaced apart from each other by the first separation structures, and extend in parallel to each other in a first horizontal direction. The second memory blocks are spaced apart from each other by the second separation structures, and extend in parallel to each other in a second horizontal direction. The first and second horizontal directions are parallel to an upper surface of the first conductive plate structure, and are perpendicular to each other.

公开(公告)号：US11716854B2

公开(公告)日：2023-08-01

申请号：US17024105

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Woosung Yang ,  Sejie Takaki

IPC: H10B43/40 ,  G11C7/18 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/43 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/40 ,  G11C7/18 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/43 ,  H10B43/10 ,  H10B43/27

Abstract: A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.

公开(公告)号：US11581333B2

公开(公告)日：2023-02-14

申请号：US17573015

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho Ahn ,  Woosung Yang ,  Joonsung Lim ,  Sungmin Hwang

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11526 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L27/11573

Abstract: An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.

公开(公告)号：US11450684B2

公开(公告)日：2022-09-20

申请号：US17007141

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Joonsung Lim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11526 ,  G11C7/18 ,  H01L23/522 ,  H01L27/11524

Abstract: A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

公开(公告)号：US11930639B2

公开(公告)日：2024-03-12

申请号：US17706426

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Dong-Sik Lee ,  Sung-Min Hwang ,  Joon-Sung Lim

IPC: H01L23/522 ,  H01L21/28 ,  H01L23/528 ,  H01L29/66 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66545 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

公开(公告)号：US20240074173A1

公开(公告)日：2024-02-29

申请号：US18300022

申请日：2023-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ahreum Lee ,  Woosung Yang ,  Jimo Gu ,  Jaeho Kim ,  Sukkang Sung

IPC: H10B41/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B41/27 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: According to some embodiments of inventive concepts, vertical nonvolatile memory devices and related methods may reduce chip size. The nonvolatile memory device may include a substrate wherein a first direction is orthogonal with respect to a surface of the substrate and wherein the substrate includes a cell array area and an extension area. A first gate structure layer on the substrate may include a plurality of first gate layers. A contact separation layer may be on the first gate structure layer on the extension area. A second gate structure layer on the first gate structure layer and on the contact separation layer may include a plurality of second gate layers. A plurality of channel structures may extend in the first direction through the first and second gate structure layers on the cell array area. A plurality of first metal contacts may extend through the first gate structure layer in the first direction between the substate and the contact separation layer in the extension area. A plurality of second metal contacts may extend through the second gate structure layer in the first direction in the extension area. The contact separation layer may be between the first plurality of metal contacts and the second plurality of metal contacts, and each of the second metal contacts may be aligned with a respective one of the first metal contacts in the first direction. The device may also include a plurality of first electrode pads and a plurality of second electrode pads. Each of the first electrode pads may extend from a sidewall of a respective one of the first metal contacts to provide electrical coupling with a respective one of the first gate layers. Each of the second electrode pads may extend from a sidewall of a respective one of the second metal contacts to provide electrical coupling with a respective one of the second gate layers.

公开(公告)号：US20230240068A1

公开(公告)日：2023-07-27

申请号：US18194258

申请日：2023-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Dong-Sik Lee

IPC: H10B41/46 ,  H01L23/528 ,  H01L23/522 ,  G11C16/08 ,  G11C7/18 ,  H10B41/10 ,  H10B41/20 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

CPC classification number: H10B41/46 ,  G11C7/18 ,  G11C16/08 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/20 ,  H10B41/48 ,  H10B43/10 ,  H10B43/20 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

公开(公告)号：US11437300B2

公开(公告)日：2022-09-06

申请号：US16989017

申请日：2020-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Jiyoung Kim ,  Jiwon Kim

IPC: H01L23/48 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate including a cell region and a connection region. The connection region includes a plurality of pad regions and a through electrode region. A horizontal conductive layer is on the substrate. A supporter is on the horizontal conductive layer. The supporter includes a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through electrode region. A connection conductive layer is between the first portion and the horizontal conductive layer. A connection mold layer is between the third portion and the horizontal conductive layer. A first buried insulation layer passing through the third portion, the connection mold layer, and the horizontal conductive layer is provided. A stacked structure is on the substrate. A through electrode passing through the first buried insulation layer is provided.

公开(公告)号：US20240194266A1

公开(公告)日：2024-06-13

申请号：US18518496

申请日：2023-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Jiyoung Kim ,  Woosung Yang ,  Dohyung Kim ,  Sukkang Sung

IPC: G11C16/08 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: G11C16/08 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a first substrate structure including a first decoder circuit region, a second decoder circuit region, and a page buffer circuit region, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a first cell structure that includes first horizontally extending gate electrodes, and a second cell structure that includes second horizontally extending gate electrodes. The second cell structure is disposed below the first cell structure. A first stair structure is disposed to one side of the first and second cell structures, and a second stair structure is disposed to a second side opposite the first side. a dummy structure is disposed below the first stair structure. First contact plugs pass through the first stair structure and the first dummy structure and are respectively connected to the first gate electrodes, and second contact plugs pass through the second stair structure and are respectively connected to the second gate electrodes.

公开(公告)号：US11996352B2

公开(公告)日：2024-05-28

申请号：US17888727

申请日：2022-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  Jiyoung Kim ,  Jiwon Kim

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H01L23/481 ,  H10B43/27

Abstract: A semiconductor device includes a substrate including a cell region and a connection region. The connection region includes a plurality of pad regions and a through electrode region. A horizontal conductive layer is on the substrate. A supporter is on the horizontal conductive layer. The supporter includes a first portion in the cell region, a second portion in the plurality of pad regions, and a third portion in the through electrode region. A connection conductive layer is between the first portion and the horizontal conductive layer. A connection mold layer is between the third portion and the horizontal conductive layer. A first buried insulation layer passing through the third portion, the connection mold layer, and the horizontal conductive layer is provided. A stacked structure is on the substrate. A through electrode passing through the first buried insulation layer is provided.