Detecting programmed word lines based on NAND string current
    11.
    发明授权
    Detecting programmed word lines based on NAND string current 有权
    基于NAND串电流检测编程字线

    公开(公告)号:US08964480B2

    公开(公告)日:2015-02-24

    申请号:US13932384

    申请日:2013-07-01

    Abstract: A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block.

    Abstract translation: 通过在所有存储单元处于导通状态时测量块中的参考组合电流(Iref)来确定NAND串块中的编程字线的数量(Nwl)。 随后,为了确定字线是否是编程字线,块中的附加组合电流(Iadd)是用施加到所选字线的分界电压来测量的。 如果Idd小于Iref至少有余量,则所选字线被确定为编程字线。 当数字相对较小时,通过使擦除验证测试相对难于通过,当数量相对较大时,Nwl可用于调整擦除操作的擦除验证测试。 或者,Nwl可用于标识块中的下一个字线进行编程。

    Pseudo block operation mode in 3D NAND
    12.
    发明授权
    Pseudo block operation mode in 3D NAND 有权
    3D NAND中的伪块操作模式

    公开(公告)号:US08913431B1

    公开(公告)日:2014-12-16

    申请号:US14274440

    申请日:2014-05-09

    Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.

    Abstract translation: 一种3D NAND堆叠非易失性存储器件,包括:包括多个非易失性存储元件的串,所述串包括通道并垂直延伸穿过所述3D堆叠非易失性存储器件的层,并且所述多个存储元件 基于组分配被细分为不同的组,每组不同组包括多个存储元件中的多个相邻存储元件; 以及控制电路,与控制电路串联连接,以执行伪块操作模式。

    Selective in-situ retouching of data in nonvolatile memory
    15.
    发明授权
    Selective in-situ retouching of data in nonvolatile memory 有权
    在非易失性存储器中选择性原位修饰数据

    公开(公告)号:US09342401B2

    公开(公告)日:2016-05-17

    申请号:US14028260

    申请日:2013-09-16

    Abstract: In a charge-storage memory array, memory cells that are programmed to a particular threshold voltage range and have subsequently lost charge have their threshold voltages restored by selectively adding charge to the memory cells. Adding charge only to memory cells with high threshold voltage ranges may sufficiently increase threshold voltages of other memory cells so that they do not require separate addition of charge.

    Abstract translation: 在电荷存储存储器阵列中,被编程到特定阈值电压范围并随后损耗电荷的存储器单元通过选择性地将电荷加到存储器单元而恢复它们的阈值电压。 仅向具有高阈值电压范围的存储单元加电荷可充分提高其它存储单元的阈值电压,从而不需要单独添加电荷。

    BLOCK REFRESH TO ADAPT TO NEW DIE TRIM SETTINGS
    16.
    发明申请
    BLOCK REFRESH TO ADAPT TO NEW DIE TRIM SETTINGS 有权
    块改装适用于新的DIE TRIM设置

    公开(公告)号:US20160099057A1

    公开(公告)日:2016-04-07

    申请号:US14507245

    申请日:2014-10-06

    CPC classification number: G11C16/10 G11C16/0483 G11C16/3459 G11C29/028

    Abstract: Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a semiconductor memory may have a first charge level and be programmed with a first trim set. The cell may be reprogrammed by raising the first charge level to a second charge level that corresponds to the cell programmed with a second trim set.

    Abstract translation: 可以提供适应调整组提前的系统,装置和方法。 修剪设置的进步可能会随着时间的推移而发生变化。 半导体存储器的单元可以具有第一充电水平并且被编程为具有第一调整组。 可以通过将第一充电电平升高到对应于用第二调整组编程的单元的第二充电水平来重新编程单元。

    System and method of determining reading voltages of a data storage device
    19.
    发明授权
    System and method of determining reading voltages of a data storage device 有权
    确定数据存储设备的读取电压的系统和方法

    公开(公告)号:US09147490B2

    公开(公告)日:2015-09-29

    申请号:US13839430

    申请日:2013-03-15

    CPC classification number: G11C16/34 G11C11/5642 G11C16/26

    Abstract: A data storage device includes a memory and a controller. In a particular embodiment, a method is performed in the data storage device. The method is performed during a read threshold voltage update operation and includes determining a first read threshold voltage of a set of storage elements of a memory according to a first technique and determining a second read threshold voltage of the set of storage elements of the memory according to a second technique. The first read threshold voltage is different from the second read threshold voltage, and the first technique is different from the second technique.

    Abstract translation: 数据存储装置包括存储器和控制器。 在特定实施例中,在数据存储装置中执行方法。 该方法在读取阈值电压更新操作期间执行,并且包括根据第一技术确定存储器的一组存储元件的第一读取阈值电压,并且根据第一技术确定存储器组的存储元件组的第二读取阈值电压, 到第二种技术。 第一读取阈值电压与第二读取阈值电压不同,并且第一技术不同于第二技术。

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