利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

78 条记录 (耗时 0.024 秒)

    Three-dimensional non-volatile memory device
    11.
    发明授权
    Three-dimensional non-volatile memory device 有权
    三维非易失性存储器件

    公开(公告)号：US09496274B2

    公开(公告)日：2016-11-15

    申请号：US14264407

    申请日：2014-04-29

    申请人： SanDisk Technologies, Inc.

    发明人： Jayavel Pachamuthu ,  Johann Alsmeier ,  Raghuveer S. Makala ,  Yao-Sheng Lee

    IPC分类号： H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/105 ,  H01L21/02 ,  H01L27/112 ,  H01L27/06 ,  H01L27/10 ,  H01L29/66 ,  H01L29/792 ,  H01L21/306

    CPC分类号： H01L27/11551 ,  H01L21/022 ,  H01L21/30604 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1052 ,  H01L27/1128 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7926

    摘要： A memory device includes a stack of material layers with a plurality of NAND strings extending through the stack, and a trench through the stack with a pair of sidewalls defining a width of the trench that is substantially constant or decreases from the top of the trench to a first depth and increases between a first depth and a second depth that is closer to the bottom of the trench than the first depth and the trench has an insulating material covering at least the trench sidewalls. Further embodiments include a memory device including a stack of material layers and an active memory cell region defined between a pair of trenches, and within the active region the stack comprises alternating layers of a first material and a second material, and outside of the active region the stack comprises alternating layers of the first material and a third material.

    摘要翻译： 存储器件包括具有延伸穿过堆叠的多个NAND串的材料层堆叠以及穿过堆叠的沟槽，该沟槽具有限定沟槽宽度的一对侧壁，所述沟槽的宽度从沟槽的顶部基本上恒定或减小， 在比第一深度更靠近沟槽底部的第一深度和第二深度之间增加第一深度并且沟槽具有覆盖至少沟槽侧壁的绝缘材料。 另外的实施例包括存储器件，其包括堆叠的材料层和限定在一对沟槽之间的有源存储器单元区域，并且在有源区域内，堆叠包括第一材料和第二材料的交替层，以及活性区域外 堆叠包括第一材料和第三材料的交替层。

    Three dimensional NAND device with semiconductor, metal or silicide floating gates and method of making thereof
    14.
    发明授权
    Three dimensional NAND device with semiconductor, metal or silicide floating gates and method of making thereof 有权
    具有半导体，金属或硅化物浮栅的三维NAND器件及其制造方法

    公开(公告)号：US09397093B2

    公开(公告)日：2016-07-19

    申请号：US13762988

    申请日：2013-02-08

    申请人： SanDisk Technologies, Inc.

    发明人： Raghuveer S. Makala ,  Johann Alsmeier

    IPC分类号： H01L21/336 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8239 ,  H01L21/28 ,  H01L21/822 ,  H01L29/788 ,  H01L27/115

    CPC分类号： H01L27/088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/8221 ,  H01L21/8239 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7889

    摘要： A method of making a monolithic three dimensional NAND string includes forming a stack of alternating layers of a first material and a second material, etching the stack to form a front side opening in the stack, selectively forming a plurality of discrete semiconductor, metal or silicide charge storage regions on portions of the second material layers exposed in the front side opening, forming a tunnel dielectric layer and semiconductor channel layer in the front side opening, etching the stack to form a back side opening in the stack, removing at least a portion of the second material layers through the back side opening to form back side recesses between the first material layers, forming a blocking dielectric in the back side recesses through the back side opening, and forming control gates over the blocking dielectric in the back side recesses through the back side opening.

    摘要翻译： 制造单片三维NAND串的方法包括形成第一材料和第二材料的交替层的堆叠，蚀刻堆叠以在堆叠中形成前侧开口，选择性地形成多个分立的半导体，金属或硅化物 在前侧开口中露出的第二材料层的部分上的电荷存储区域，在前侧开口中形成隧道介电层和半导体沟道层，蚀刻堆叠以在堆叠中形成背侧开口，去除至少一部分 通过后侧开口形成第二材料层，以在第一材料层之间形成后侧凹槽，在后侧开口中通过背侧开口形成阻挡电介质，并且在后侧凹部中的阻挡电介质上方形成控制栅极 背面开口。

    THREE-DIMENSIONAL MEMORY STRUCTURE WITH MULTI-COMPONENT CONTACT VIA STRUCTURE AND METHOD OF MAKING THEREOF
    16.
    发明申请
    THREE-DIMENSIONAL MEMORY STRUCTURE WITH MULTI-COMPONENT CONTACT VIA STRUCTURE AND METHOD OF MAKING THEREOF 有权
    通过结构与多组分接触的三维存储结构及其制备方法

    公开(公告)号：US20160141294A1

    公开(公告)日：2016-05-19

    申请号：US14926347

    申请日：2015-10-29

    申请人： SANDISK TECHNOLOGIES INC.

    发明人： Somesh Peri ,  Sateesh Koka ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Matthias Baenninger ,  Jayavel Pachamuthu ,  Johann Alsmeier

    IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/792

    CPC分类号： H01L27/1157 ,  H01L21/28512 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/76877 ,  H01L23/53266 ,  H01L27/11582 ,  H01L29/66553 ,  H01L29/78

    摘要： A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region. At least one conductive material portion can be formed in the remaining volume of the contact trench to form a contact via structure. Alternatively or additionally, a contact via structure can include a tensile stress-generating portion and a conductive material portion. In case the contact via structure is formed through an alternating stack of insulating layers and electrically conductive layers that include a compressive stress-generating material, the tensile stress-generating portion can at least partially cancel the compressive stress generated by the electrically conductive layers. The conductive material portion of the contact via structure can include a metallic material or a doped semiconductor material.

    摘要翻译： 接触通孔结构可以包括通过在接触沟槽的底部的半导体表面上选择性沉积钌而形成的钌部分。 含钌部分可以降低与下掺杂半导体区域的界面处的接触电阻。 可以在接触沟槽的剩余容积中形成至少一个导电材料部分以形成接触通孔结构。 或者或另外，接触通孔结构可以包括拉伸应力产生部分和导电材料部分。 在接触通孔结构通过绝缘层的交替堆叠和包括压缩应力产生材料的导电层形成的情况下，拉伸应力产生部分可以至少部分地抵消由导电层产生的压缩应力。 接触通孔结构的导电材料部分可以包括金属材料或掺杂的半导体材料。

    Three dimensional NAND device and method of making thereof
    17.
    发明授权
    Three dimensional NAND device and method of making thereof 有权
    三维NAND器件及其制造方法

    公开(公告)号：US09236396B1

    公开(公告)日：2016-01-12

    申请号：US14539307

    申请日：2014-11-12

    申请人： SanDisk Technologies, Inc.

    发明人： Sateesh Koka ,  Senaka Kanakamedala ,  Yanli Zhang ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  George Matamis ,  Wei Zhao

    IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49

    CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11556 ,  H01L29/495 ,  H01L29/517 ,  H01L29/7883

    摘要： A monolithic three dimensional NAND string includes a semiconductor channel, at least one end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. The NAND string also includes a memory film located between the semiconductor channel and the plurality of control gate electrodes and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. The NAND string also includes a plurality of discrete cover silicon oxide segments located between the memory film and each respective clam-shaped portion of the blocking dielectric containing a respective control gate electrode. Each of the plurality of cover silicon oxide segments has curved upper and lower sides and substantially straight vertical sidewalls.

    摘要翻译： 单片三维NAND串包括半导体沟道，半导体沟道的至少一个端部基本上垂直于衬底的主表面延伸，以及基本上平行于衬底的主表面延伸的多个控制栅电极。 NAND串还包括位于半导体通道和多个控制栅极电极之间的记忆膜，以及包含多个蛤状部分的阻挡电介质，每个蛤状部分具有通过垂直部分连接的两个水平部分。 NAND串还包括位于存储器膜和阻挡电介质的每个相应蛤状部分之间的多个分立的覆盖氧化硅段，其包含相应的控制栅电极。 多个覆盖氧化硅段中的每一个具有弯曲的上侧和下侧以及基本上直的垂直侧壁。

    Method of making a vertical NAND device using sequential etching of multilayer stacks
    18.
    发明授权
    Method of making a vertical NAND device using sequential etching of multilayer stacks 有权
    使用多层堆叠的顺序蚀刻制造垂直NAND器件的方法

    公开(公告)号：US08946023B2

    公开(公告)日：2015-02-03

    申请号：US13933743

    申请日：2013-07-02

    申请人： SanDisk Technologies, Inc.

    发明人： Raghuveer S. Makala ,  Yao-Sheng Lee ,  Jayavel Pachamuthu ,  Johann Alsmeier ,  Henry Chien

    IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/822 ,  H01L27/06 ,  H01L29/788 ,  H01L29/792 ,  H01L29/66

    CPC分类号： H01L27/11582 ,  H01L21/822 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

    摘要翻译： 制造垂直NAND器件的方法包括在衬底上形成存储器堆叠的下部，在存储堆的下部形成存储器开口的下部，并至少部分地填充存储器开口的下部， 牺牲材料。 该方法还包括在存储器堆叠的下部并在牺牲材料的上方形成存储器堆叠的上部，在存储器堆叠的上部形成存储器开口的上部部分，以将下部的牺牲材料露出 部分存储器开口，去除牺牲材料以将存储器开口的下部与存储器开口的相应上部连接以形成连续的存储器开口，并在每个连续的存储器开口中形成半导体通道。

    THREE DIMENSIONAL NAND DEVICE WITH SEMICONDUCTOR, METAL OR SILICIDE FLOATING GATES AND METHOD OF MAKING THEREOF
    19.
    发明申请
    THREE DIMENSIONAL NAND DEVICE WITH SEMICONDUCTOR, METAL OR SILICIDE FLOATING GATES AND METHOD OF MAKING THEREOF 有权
    具有半导体，金属或二氧化硅浮动栅的三维NAND器件及其制造方法

    公开(公告)号：US20140225181A1

    公开(公告)日：2014-08-14

    申请号：US13762988

    申请日：2013-02-08

    申请人： SANDISK TECHNOLOGIES, INC.

    发明人： Raghuveer S. Makala ,  Johann Alsmeier

    IPC分类号： H01L27/088 ,  H01L29/66

    CPC分类号： H01L27/088 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/8221 ,  H01L21/8239 ,  H01L27/11556 ,  H01L29/66825 ,  H01L29/7889

    摘要： A method of making a monolithic three dimensional NAND string includes forming a stack of alternating layers of a first material and a second material, etching the stack to form a front side opening in the stack, selectively forming a plurality of discrete semiconductor, metal or silicide charge storage regions on portions of the second material layers exposed in the front side opening, forming a tunnel dielectric layer and semiconductor channel layer in the front side opening, etching the stack to form a back side opening in the stack, removing at least a portion of the second material layers through the back side opening to form back side recesses between the first material layers, forming a blocking dielectric in the back side recesses through the back side opening, and forming control gates over the blocking dielectric in the back side recesses through the back side opening.

    摘要翻译： 制造单片三维NAND串的方法包括形成第一材料和第二材料的交替层的堆叠，蚀刻堆叠以在堆叠中形成前侧开口，选择性地形成多个分立的半导体，金属或硅化物 在前侧开口中露出的第二材料层的部分上的电荷存储区域，在前侧开口中形成隧道介电层和半导体沟道层，蚀刻堆叠以在堆叠中形成背侧开口，去除至少一部分 通过后侧开口形成第二材料层，以在第一材料层之间形成后侧凹槽，在后侧开口中通过背侧开口形成阻挡电介质，并且在后侧凹部中的阻挡电介质上方形成控制栅极 背面开口。