公开(公告)号：US20080236878A1

公开(公告)日：2008-10-02

申请号：US12076989

申请日：2008-03-26

申请人： Seung Eun Lee ,  Yul Kyo Chung ,  Jung Won Lee ,  In Hyung Lee ,  Byung Ik Song

发明人： Seung Eun Lee ,  Yul Kyo Chung ,  Jung Won Lee ,  In Hyung Lee ,  Byung Ik Song

IPC分类号： H05K1/18 ,  H01G4/10 ,  H01G7/00

CPC分类号： H05K1/162 ,  H01G4/105 ,  H01G4/33 ,  H05K2201/0175 ,  H05K2201/0179 ,  Y10T29/435

摘要： There is provided a thin film capacitor and a capacitor-embedded printed board improved in leakage current characteristics. A dielectric layer is formed of a BiZnNb-based amorphous metal oxide with a predetermined dielectric constant without being heat treated at a high temperature, and metallic phase bismuth of the BiZnNb-based amorphous metal oxide is adjusted in content to attain a desired dielectric constant. Also, another dielectric layer having a different content of metallic phase bismuth may be formed. The thin film capacitor including: a first electrode; a dielectric layer including a first dielectric film formed on the first electrode, the dielectric layer comprising a BiZnNb-based amorphous metal oxide; and a second electrode formed on the dielectric layer, wherein the BiZnNb-based amorphous metal oxide contains metallic phase bismuth.

摘要翻译： 提供了薄膜电容器和电容器嵌入式印刷电路板，改善了漏电流特性。 电介质层由具有预定介电常数的BiZnNb基非晶态金属氧化物形成，而不在高温下进行热处理，并且将BiZnNb基非晶态金属氧化物的金属相铋的含量调节到所需的介电常数。 此外，可以形成具有不同金属相铋含量的另一介质层。 所述薄膜电容器包括：第一电极; 介电层，包括形成在所述第一电极上的第一电介质膜，所述电介质层包含BiZnNb基非晶态金属氧化物; 以及形成在所述电介质层上的第二电极，其中所述BiZnNb基非晶态金属氧化物含有金属相铋。

公开(公告)号：US07943858B2

公开(公告)日：2011-05-17

申请号：US12076989

申请日：2008-03-26

申请人： Seung Eun Lee ,  Yul Kyo Chung ,  Jung Won Lee ,  In Hyung Lee ,  Byung Ik Song

发明人： Seung Eun Lee ,  Yul Kyo Chung ,  Jung Won Lee ,  In Hyung Lee ,  Byung Ik Song

IPC分类号： H05K1/16

CPC分类号： H05K1/162 ,  H01G4/105 ,  H01G4/33 ,  H05K2201/0175 ,  H05K2201/0179 ,  Y10T29/435

摘要： There is provided a thin film capacitor and a capacitor-embedded printed board improved in leakage current characteristics. A dielectric layer is formed of a BiZnNb-based amorphous metal oxide with a predetermined dielectric constant without being heat treated at a high temperature, and metallic phase bismuth of the BiZnNb-based amorphous metal oxide is adjusted in content to attain a desired dielectric constant. Also, another dielectric layer having a different content of metallic phase bismuth may be formed. The thin film capacitor including: a first electrode; a dielectric layer including a first dielectric film formed on the first electrode, the dielectric layer comprising a BiZnNb-based amorphous metal oxide; and a second electrode formed on the dielectric layer, wherein the BiZnNb-based amorphous metal oxide contains metallic phase bismuth.

摘要翻译： 提供了薄膜电容器和电容器嵌入式印刷电路板，改善了漏电流特性。 电介质层由具有预定介电常数的BiZnNb基非晶态金属氧化物形成，而不在高温下进行热处理，并且将BiZnNb基非晶态金属氧化物的金属相铋的含量调节到所需的介电常数。 此外，可以形成具有不同金属相铋含量的另一介质层。 所述薄膜电容器包括：第一电极; 介电层，包括形成在所述第一电极上的第一电介质膜，所述电介质层包含BiZnNb基非晶态金属氧化物; 以及形成在所述电介质层上的第二电极，其中所述BiZnNb基非晶态金属氧化物含有金属相铋。

公开(公告)号：US07737529B2

公开(公告)日：2010-06-15

申请号：US11582954

申请日：2006-10-19

申请人： Jin Seok Moon ,  Seung Eun Lee ,  Hyung Mi Jung ,  Yul Kyo Chung ,  Seung Hyun Sohn

发明人： Jin Seok Moon ,  Seung Eun Lee ,  Hyung Mi Jung ,  Yul Kyo Chung ,  Seung Hyun Sohn

IPC分类号： H01L29/00

CPC分类号： H05K1/162 ,  H05K3/388 ,  H05K2201/0175 ,  H05K2201/0179

摘要： The invention provides a PCB with a thin film capacitor embedded therein and a method for manufacturing the same. The PCB includes a lower electrode formed on an insulating substrate; an amorphous paraelectric film formed on the lower electrode via low temperature film formation; a buffer layer formed on the amorphous paraelectric film; a metal seed layer formed on the buffer layer; and an upper electrode formed on the metal seed layer.

摘要翻译： 本发明提供一种其中嵌有薄膜电容器的PCB及其制造方法。 PCB包括形成在绝缘基板上的下电极; 通过低温成膜形成在下电极上的非晶顺电膜; 形成在所述非晶正电介质膜上的缓冲层; 形成在缓冲层上的金属种子层; 以及形成在金属籽晶层上的上电极。

公开(公告)号：US20080158777A1

公开(公告)日：2008-07-03

申请号：US11979770

申请日：2007-11-08

申请人： Seung Hyun Sohn ,  Yul Kyo Chung ,  Seung Eun Lee ,  Yee Na Shin

发明人： Seung Hyun Sohn ,  Yul Kyo Chung ,  Seung Eun Lee ,  Yee Na Shin

IPC分类号： H01G4/06 ,  H01G4/00

CPC分类号： H05K1/162 ,  H01G4/232 ,  H01G4/30 ,  H01G4/33 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09781

摘要： There are provided a capacitor and a thin film capacitor-embedded multi-layer wiring board. The capacitor includes: first and second electrodes connected to first and second polarities; a dielectric layer formed therebetween; and at least one floating electrode disposed inside the dielectric layer and having overlaps with the first and second electrodes. The wiring board includes: an insulating body having a plurality of insulating layers thereon; a plurality of conductive patterns and conductive vias formed on the insulating layers, respectively, to constitute an interlayer circuit; and a thin film capacitor embedded in the insulating body, wherein the thin film capacitor includes a first electrode layer, a first dielectric layer, at least one floating electrode layer, a second dielectric layer and a second electrode layer sequentially formed, and wherein the first and second electrode layers are connected to the interlayer circuit and the floating electrode layer is not directly connected thereto.

摘要翻译： 提供电容器和薄膜电容器嵌入式多层布线板。 电容器包括：连接到第一和第二极性的第一和第二电极; 在它们之间形成介电层; 以及至少一个浮置电极，其布置在电介质层的内部并与第一和第二电极重叠。 布线板包括：绝缘体，其上具有多个绝缘层; 分别形成在绝缘层上的多个导电图案和导电通孔，以构成层间电路; 以及嵌入在所述绝缘体中的薄膜电容器，其中所述薄膜电容器包括依次形成的第一电极层，第一电介质层，至少一个浮置电极层，第二电介质层和第二电极层，并且其中所述第一电极层 并且第二电极层连接到层间电路，并且浮动电极层不直接连接到其上。

公开(公告)号：US20080158770A1

公开(公告)日：2008-07-03

申请号：US12000125

申请日：2007-12-10

申请人： In Hyung Lee ,  Yul Kyo Chung ,  Bae Kyun Kim ,  Seung Eun Lee ,  Jung Won Lee

发明人： In Hyung Lee ,  Yul Kyo Chung ,  Bae Kyun Kim ,  Seung Eun Lee ,  Jung Won Lee

IPC分类号： H01G4/00 ,  H05K3/30

CPC分类号： H05K1/162 ,  H01G4/005 ,  H01G4/33 ,  H05K3/046 ,  H05K2201/0108 ,  H05K2201/0175 ,  H05K2203/016 ,  H05K2203/0528 ,  H05K2203/0537 ,  H05K2203/107 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155

摘要： A method of manufacturing a circuit board embedding a thin film capacitor, the method including: forming a sacrificial layer on a first substrate; forming a dielectric layer on the sacrificial layer; forming a first electrode layer on the dielectric layer; disposing the first substrate on the second substrate in such a way that the first electrode layer is bonded to a top of a second substrate; decomposing the sacrificial layer by irradiating a laser beam onto the sacrificial layer through the first substrate; separating the first substrate from the second substrate; and forming a second electrode layer on the dielectric layer.

摘要翻译： 一种制造嵌入薄膜电容器的电路板的方法，所述方法包括：在第一基板上形成牺牲层; 在所述牺牲层上形成介电层; 在所述电介质层上形成第一电极层; 将第一基板设置在第二基板上，使得第一电极层接合到第二基板的顶部; 通过经由所述第一基板将激光束照射到所述牺牲层上来分解所述牺牲层; 将第一基板与第二基板分离; 以及在所述电介质层上形成第二电极层。

公开(公告)号：US09087837B2

公开(公告)日：2015-07-21

申请号：US13572833

申请日：2012-08-13

申请人： Doo Hwan Lee ,  Tae Sung Jeong ,  Yul Kyo Chung

发明人： Doo Hwan Lee ,  Tae Sung Jeong ,  Yul Kyo Chung

IPC分类号： H01L23/28 ,  H01L21/52 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L21/768 ,  H01L23/544 ,  H01L21/54 ,  H01L21/78

CPC分类号： H01L21/52 ,  H01L21/54 ,  H01L21/561 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/00

摘要： Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

摘要翻译： 这里公开了一种半导体封装及其制造方法，所述半导体封装包括：模制构件，其中形成有空腔; 安装在腔体中的装置; 绝缘构件，其形成在所述空腔内并且在所述模制构件和所述装置之上和/或之下; 形成在所述绝缘构件上的电路层，并且包括与所述装置电连接的通孔和连接垫; 形成在电路层上的阻焊层，并且具有暴露连接焊盘的上部的开口; 以及形成在开口中的焊球。

公开(公告)号：US08802999B2

公开(公告)日：2014-08-12

申请号：US13478802

申请日：2012-05-23

申请人： Jong In Ryu ,  Yul Kyo Chung ,  Tae Sung Jeong

发明人： Jong In Ryu ,  Yul Kyo Chung ,  Tae Sung Jeong

IPC分类号： H05K1/09

CPC分类号： H05K1/185 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/12042 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K2201/10477 ,  H05K2203/1461 ,  H01L2924/00

摘要： An embedded printed circuit board (PCB) includes: a copper foil laminate; an internal electronic component inserted into the copper foil laminate; a first circuit pattern formed on a surface of the internal electronic component; and a second circuit pattern formed on the copper foil laminate.

摘要翻译： 嵌入式印刷电路板（PCB）包括：铜箔层压板; 插入铜箔层压体中的内部电子部件; 形成在所述内部电子部件的表面上的第一电路图案; 以及形成在铜箔层叠体上的第二电路图案。

公开(公告)号：US20120017435A1

公开(公告)日：2012-01-26

申请号：US13200983

申请日：2011-10-06

申请人： Seung Hyun Sohn ,  Yul Kyo Chung ,  Byoung Chan Kim ,  Moon Il Kim ,  Kwan Kyu Kim ,  Yee Na Shin

发明人： Seung Hyun Sohn ,  Yul Kyo Chung ,  Byoung Chan Kim ,  Moon Il Kim ,  Kwan Kyu Kim ,  Yee Na Shin

IPC分类号： H05K3/30

CPC分类号： H05K1/185 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K3/025 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2203/0152 ,  H05K2203/063 ,  H05K2203/1152 ,  H05K2203/1469 ,  Y10T29/49124 ,  Y10T29/4913 ,  H01L2924/00

摘要： A method of manufacturing a PCB having electronic components embedded therein, including: preparing a copper foil layer including a thin copper foil coated with a resin layer; fixing electronic components onto the resin layer; forming a core layer in which the electronic components are embedded; forming internal layer circuits which are electrically connected to the electronic components; forming an insulating layer on the internal layer circuits; and forming external layer circuits on the insulating layer such that the external layer circuits are electrically connected to the internal layer circuits.

摘要翻译： 一种制造其中嵌有电子元件的PCB的方法，包括：制备包括涂覆有树脂层的薄铜箔的铜箔层; 将电子部件固定到树脂层上; 形成其中嵌入有电子部件的芯层; 形成电连接到所述电子部件的内层电路; 在内层电路上形成绝缘层; 以及在所述绝缘层上形成外层电路，使得所述外层电路电连接到所述内层电路。

公开(公告)号：US08049117B2

公开(公告)日：2011-11-01

申请号：US12466841

申请日：2009-05-15

申请人： Jung Won Lee ,  Yul Kyo Chung ,  In Hyung Lee

发明人： Jung Won Lee ,  Yul Kyo Chung ,  In Hyung Lee

IPC分类号： H05K1/16

CPC分类号： H05K1/162 ,  H01G4/33 ,  H01G13/00 ,  H01L21/4857 ,  H01L23/50 ,  H01L2924/0002 ,  H05K2201/0108 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2203/016 ,  H05K2203/107 ,  Y10T29/43 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method for manufacturing a printed circuit board with a capacitor embedded therein which has a dielectric film using laser lift off, and a capacitor manufactured thereby. In the method, a dielectric film is formed on a transparent substrate and heat-treated. A first conductive layer is formed on the heat-treated dielectric film. A laser beam is irradiated onto a stack formed, from below the transparent substrate, to separate the transparent substrate from the stack. After the transparent substrate is separated from the stack, a second conductive layer is formed with a predetermined pattern on the dielectric film. Also, an insulating layer and a third conductive layer are formed on the first and second conductive layers to alternate with each other in a predetermined number.

摘要翻译： 一种制造其中嵌有电容器的印刷电路板的方法，其中具有使用激光剥离的电介质膜，以及由此制造的电容器。 在该方法中，在透明基板上形成电介质膜并进行热处理。 在热处理电介质膜上形成第一导电层。 将激光束照射到从透明基板的下方形成的堆叠上，以将透明基板与堆叠分离。 在将透明基板与堆叠体分离之后，在电介质膜上形成具有预定图案的第二导电层。 此外，绝缘层和第三导电层形成在第一和第二导电层上，以预定数量相互交替。

公开(公告)号：US07812465B2

公开(公告)日：2010-10-12

申请号：US12232528

申请日：2008-09-18

申请人： Jae Kul Lee ,  Yul Kyo Chung

发明人： Jae Kul Lee ,  Yul Kyo Chung

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L24/02 ,  H01L24/16 ,  H01L24/25 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/19 ,  H01L2224/83121 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/0269 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4679 ,  H05K2201/09918

摘要： Disclosed is a semiconductor chip having an alignment mark which is formed on the surface of the semiconductor chip where no external connection bump is formed, and which has the position information of the external connection bump. A method of manufacturing the semiconductor chip having an alignment mark is also provided. Because the semiconductor chip includes the alignment mark having the position information of the external connection bump, the external connection bump is matched with a via which is formed in the external circuit layer of a printed circuit board including the semiconductor chip, thus improving electrical connection with the printed circuit board, and increasing the reliability of the printed circuit board including the semiconductor chip.

摘要翻译： 公开了一种具有对准标记的半导体芯片，其形成在半导体芯片的没有形成外部连接凸块的表面上，并具有外部连接凸块的位置信息。 还提供了具有对准标记的制造半导体芯片的方法。 由于半导体芯片包括具有外部连接凸块的位置信息的对准标记，所以外部连接凸块与形成在包括半导体芯片的印刷电路板的外部电路层中的通路匹配，从而改善与 印刷电路板，并且增加包括半导体芯片的印刷电路板的可靠性。