公开(公告)号：US09899235B2

公开(公告)日：2018-02-20

申请号：US15293858

申请日：2016-10-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Ching Ho ,  Ying-Chou Tsai ,  Sheng-Che Huang

IPC: H01L21/48 ,  H01L23/00 ,  H05K3/20 ,  H05K3/34 ,  H05K3/40 ,  H01L23/498 ,  H01L21/683 ,  H05K3/06 ,  H05K3/46

CPC classification number: H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/81193 ,  H05K3/064 ,  H05K3/205 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4682 ,  H05K2201/0376 ,  Y02P70/613 ,  Y10T29/49158

Abstract: A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.

公开(公告)号：US20170294372A1

公开(公告)日：2017-10-12

申请号：US15632669

申请日：2017-06-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chi-Ching Ho ,  Shao-Tzu Tang ,  Yu-Che Liu ,  Ying-Chou Tsai

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2224/13099 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.

公开(公告)号：US09165789B2

公开(公告)日：2015-10-20

申请号：US14643444

申请日：2015-03-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Ching Ho ,  Yu-Chih Yu ,  Ying-Chou Tsai

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/48 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/83 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.

Abstract translation: 一种封装衬底的制造方法，包括：提供具有第一表面和与第一表面相对的第二表面的金属板，其中第一表面具有多个用于在其间限定第一芯电路层的第一开口，第二表面具有 用于在其间限定第二芯电路层的多个第二开口，所述第一开口和所述第二开口中的每一个具有宽的外部部分和窄的内部部分，并且每个所述第二开口的内部部分与所述第二开口的内部部分连通 第一开口中的对应的一个; 在第一开口中形成第一密封剂; 在所述第二开口中形成第二密封剂; 以及在第一密封剂和第一核心电路层上形成表面电路层。

公开(公告)号：US20150187603A1

公开(公告)日：2015-07-02

申请号：US14643444

申请日：2015-03-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Ching Ho ,  Yu-Chih Yu ,  Ying-Chou Tsai

IPC: H01L21/48 ,  H01L21/56

CPC classification number: H01L21/48 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/83 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.

Abstract translation: 一种封装衬底的制造方法，包括：提供具有第一表面和与第一表面相对的第二表面的金属板，其中第一表面具有多个用于在其间限定第一芯电路层的第一开口，第二表面具有 用于在其间限定第二芯电路层的多个第二开口，所述第一开口和所述第二开口中的每一个具有宽的外部部分和窄的内部部分，并且每个所述第二开口的内部部分与所述第二开口的内部部分连通 第一开口中的对应的一个; 在第一开口中形成第一密封剂; 在所述第二开口中形成第二密封剂; 以及在第一密封剂和第一核心电路层上形成表面电路层。

公开(公告)号：US20140315353A1

公开(公告)日：2014-10-23

申请号：US14322372

申请日：2014-07-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Ching Ho ,  Yu-Chih Yu ,  Ying-Chou Tsai

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/48 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/83 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; a first encapsulant in the first openings; a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.

Abstract translation: 一种封装衬底的制造方法，包括：提供具有第一表面和与第一表面相对的第二表面的金属板，其中第一表面具有多个用于在其间限定第一芯电路层的第一开口，第二表面具有 用于在其间限定第二芯电路层的多个第二开口，所述第一开口和所述第二开口中的每一个具有宽的外部部分和窄的内部部分，并且每个所述第二开口的内部部分与所述第二开口的内部部分连通 第一开口中的对应的一个; 第一开口中的第一密封剂; 在第二开口中的第二密封剂; 以及在第一密封剂和第一核心电路层上形成表面电路层。

公开(公告)号：US20200328166A1

公开(公告)日：2020-10-15

申请号：US16534385

申请日：2019-08-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Jung Tsai ,  Ching-Chia Chen ,  Ying-Chou Tsai

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01Q1/24 ,  H01Q9/04 ,  H01Q1/38

Abstract: An electronic package and a method for fabricating the same are provided. A plurality of electronic components are disposed in a packaging structure. At least one antenna structure is stacked via a plurality of conductive elements on the packaging structure. The antenna structure is electrically connected to at least one of the electronic components. The electronic components have different radio frequencies. In mass production, the antenna structures of different antenna types are stacked on the packaging structure, and a radio frequency product of various frequencies can be produced. Radio frequency chips of different frequencies need not be fabricated into a variety of individual packaging modules. Therefore, the production cost is reduced, and the production speed is increased.

公开(公告)号：US09991197B2

公开(公告)日：2018-06-05

申请号：US15632669

申请日：2017-06-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chia-Cheng Chen ,  Chi-Ching Ho ,  Shao-Tzu Tang ,  Yu-Che Liu ,  Ying-Chou Tsai

IPC: H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2221/68345 ,  H01L2224/05554 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48159 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/35121 ,  H01L2224/13099 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods.

公开(公告)号：US20180068896A1

公开(公告)日：2018-03-08

申请号：US15704388

申请日：2017-09-14

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Chang-Yi Lan ,  Ying-Chou Tsai

IPC: H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/568 ,  H01L22/12 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00015 ,  H01L2924/1816 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/20 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/81

Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.

公开(公告)号：US09805979B2

公开(公告)日：2017-10-31

申请号：US14624642

申请日：2015-02-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Chang-Yi Lan ,  Ying-Chou Tsai

IPC: H01L23/28 ,  H01L21/78 ,  H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/568 ,  H01L22/12 ,  H01L23/3114 ,  H01L23/3157 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/1148 ,  H01L2224/1191 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00015 ,  H01L2924/1816 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/20 ,  H01L21/56 ,  H01L21/304 ,  H01L2224/81

Abstract: An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface opposite to the active surface, and a side surface adjacent to and connecting the active and inactive surfaces; a plurality of conductive elements formed on the electrode pads of the electronic element; and an encapsulant covering the active and side surfaces of the electronic element and portions of side surfaces of the conductive elements and exposing the inactive surface of the electronic element. Therefore, the invention enhances the structural strength of the active surface of the electronic element so as to prevent cracking of the electronic element and hence avoid delamination of the conductive elements from the electronic element.

公开(公告)号：US20170273185A1

公开(公告)日：2017-09-21

申请号：US15615158

申请日：2017-06-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shao-Tzu Tang ,  Ying-Chou Tsai

IPC: H05K3/00 ,  H05K1/11

CPC classification number: H05K3/0014 ,  H05K1/116 ,  H05K2201/09118 ,  H05K2201/09545 ,  H05K2201/09563 ,  Y10T29/49167

Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.