公开(公告)号：US20190088608A1

公开(公告)日：2019-03-21

申请号：US15954254

申请日：2018-04-16

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Salvatore Frank Pavone ,  Christopher Daniel Manack

IPC: H01L23/00 ,  C25D5/12

CPC classification number: H01L24/11 ,  C25D3/30 ,  C25D3/38 ,  C25D3/56 ,  C25D3/562 ,  C25D3/60 ,  C25D5/022 ,  C25D5/10 ,  C25D5/12 ,  C25D5/18 ,  C25D5/505 ,  C25D7/00 ,  C25D7/123 ,  H01L21/288 ,  H01L23/49524 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05096 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13284 ,  H01L2224/13582 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13639 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1368 ,  H01L2224/13684 ,  H01L2224/13693 ,  H01L2224/16245 ,  H01L2224/16503 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01042 ,  H01L2924/01027 ,  H01L2924/01028

Abstract: A microelectronic device includes a reflow structure. The reflow structure has a copper-containing member and a solder member, and a barrier layer between them. The barrier layer has metal grains, with a diffusion barrier filler between the metal grains. The metal grains include at least a first metal and a second metal, each selected from nickel, cobalt, lanthanum, and cerium, with each having a concentration in the metal grains of at least 10 weight percent. The diffusion barrier filler includes at least a third metal, selected from tungsten and molybdenum. A combined concentration of tungsten and molybdenum in the diffusion barrier filler is higher than in the metal grains to provide a desired resistance to diffusion of copper. The barrier layer includes 2 weight percent to 15 weight percent of the combined concentration of tungsten, and molybdenum. A bump bond structure and a lead frame package are disclosed.

公开(公告)号：US11876065B2

公开(公告)日：2024-01-16

申请号：US17491496

申请日：2021-09-30

Applicant: Texas Instruments Incorporated

Inventor： Katleen Fajardo Timbol ,  Salvatore Frank Pavone ,  Rafael Jose Lizares Guevara

IPC: H01L23/00 ,  H01L21/027

CPC classification number: H01L24/13 ,  H01L21/027 ,  H01L24/04 ,  H01L24/11 ,  H01L2221/1068 ,  H01L2224/022 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/014 ,  H01L2924/177

Abstract: In a described example, an apparatus includes: a semiconductor die having a device side surface; bond pads on the semiconductor die on the device side surface; post connects having a proximate end on the bond pads and extending from the bond pads to a distal end, the diameter of the post connects at the proximate end being the same as the diameter of the post connects at the distal end; polyimide material covering sides of the post connects and covering at least a portion of the bond pads; and solder bumps on the distal end of the post connects.

公开(公告)号：US11855024B2

公开(公告)日：2023-12-26

申请号：US17463047

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qiao Chen ,  Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Patrick Francis Thompson ,  Jonathan Andrew Montoya ,  Salvatore Frank Pavone

IPC: H01L23/00

CPC classification number: H01L24/09 ,  H01L24/25 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/09181 ,  H01L2224/2541 ,  H01L2224/73209 ,  H01L2224/81801

Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.

公开(公告)号：US20220415762A1

公开(公告)日：2022-12-29

申请号：US17359635

申请日：2021-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel Manack ,  Jonathan Andrew Montoya ,  Steven Alfred Kummerl ,  Salvatore Frank Pavone

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/31 ,  H01L23/60 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor die including terminals, a plurality of leads, at least some of the leads being electrically coupled to the terminals within the semiconductor package, a sensor on a surface of the semiconductor die, laser shielding forming a perimeter around the sensor on the surface of the semiconductor die, and a mold compound surrounding the semiconductor die except for an area inside the perimeter on the surface of the semiconductor die such that the sensor is exposed to an external environment.

公开(公告)号：US11410947B2

公开(公告)日：2022-08-09

申请号：US16721546

申请日：2019-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

Abstract: A package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer. The package is a wafer chip scale package (WCSP). The package further includes a solder ball attached to the redistribution layer.

公开(公告)号：US20200161210A1

公开(公告)日：2020-05-21

申请号：US16193089

申请日：2018-11-16

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/373 ,  H01L21/288 ,  H01L21/285 ,  H01L21/78 ,  H01L21/768 ,  C23C14/16 ,  C23C18/38 ,  C25D3/46 ,  C25D3/38

Abstract: Described examples include a process that includes forming a diffusion barrier layer on a backside of a semiconductor wafer. The process also includes forming a seed copper layer on the diffusion barrier layer. The process also includes forming a copper layer on the seed copper layer. The process also includes immersion plating a silver layer on the copper layer.

公开(公告)号：US20190259717A1

公开(公告)日：2019-08-22

申请号：US15901631

申请日：2018-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01L21/78

Abstract: A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame. In addition the method includes wire bonding the leads of a lead frame to the copper leads of the semiconductor die and then encapsulating the die in molding compound.

公开(公告)号：US20190109074A1

公开(公告)日：2019-04-11

申请号：US15984343

申请日：2018-05-19

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone

IPC: H01L23/495 ,  H01L23/532 ,  H01L23/49 ,  H01L23/492 ,  H01L23/00

Abstract: A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

公开(公告)号：US20240194574A1

公开(公告)日：2024-06-13

申请号：US18585629

申请日：2024-02-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Yogesh Kumar Ramadass ,  Salvatore Frank Pavone ,  Mahmud Halim Chowdhury

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49589 ,  H01L23/4951 ,  H01L23/49524 ,  H01L24/32 ,  H01L24/73 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/16245 ,  H01L2224/32265 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/9211 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.

公开(公告)号：US20230005807A1

公开(公告)日：2023-01-05

申请号：US17931828

申请日：2022-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Keith Edward Johnson ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065

Abstract: A device includes a semiconductor die including a via, a layer of titanium tungsten (TiW) in contact with the via, and a copper pillar including a top portion and a bottom portion. The bottom portion is in contact with the layer of TiW. The copper pillar includes interdiffused zinc within the bottom portion.