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118 条记录 (耗时 0.033 秒)

    Semiconductor package
    11.
    发明授权
    Semiconductor package 有权
    半导体封装

    公开(公告)号：US08823153B2

    公开(公告)日：2014-09-02

    申请号：US13584743

    申请日：2012-08-13

    申请人： Tae Hoon Kim ,  Seog Moon Choi

    发明人： Tae Hoon Kim ,  Seog Moon Choi

    IPC分类号： H01L23/48

    CPC分类号： H01L23/3107 ,  H01L21/563 ,  H01L23/4334 ,  H01L23/49537 ,  H01L23/49575 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein is a semiconductor package. The semiconductor package includes: semiconductor elements, a first heat dissipation substrate formed under the semiconductor elements, a first lead frame electrically connecting the lower portions of the semiconductor elements to an upper portion of the first heat dissipation substrate, a second heat dissipation substrate formed over the semiconductor elements, and a second lead frame having a protrusion formed to be protruded from a lower surface thereof and electrically connecting the upper portions of the semiconductor elements to a lower portion of the second heat dissipation substrate.

    摘要翻译： 这里公开了半导体封装。 半导体封装包括：半导体元件，形成在半导体元件下的第一散热基板，将半导体元件的下部电连接到第一散热基板的上部的第一引线框架，形成在第一散热基板上的第二散热基板 所述半导体元件和具有突起的第二引线框架，所述突起形成为从其下表面突出并将所述半导体元件的上部电连接到所述第二散热基板的下部。

    SEMICONDUCTOR PACKAGE
    13.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开
    半导体封装

    公开(公告)号：US20130154069A1

    公开(公告)日：2013-06-20

    申请号：US13584143

    申请日：2012-08-13

    申请人： Tae Hoon Kim ,  Seog Moon Choi

    发明人： Tae Hoon Kim ,  Seog Moon Choi

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49537 ,  H01L23/4334 ,  H01L23/49575 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed herein is a semiconductor package, including: a first heat dissipation substrate; a first lead frame that is formed on the first heat dissipation substrate by patterning; a first semiconductor device formed on the first lead frame; a second semiconductor device that is stacked on the first semiconductor device; a second lead frame that is patterned and bonded to the second semiconductor device; and a second heat dissipation substrate formed on the first lead frame.

    摘要翻译： 本文公开了一种半导体封装，包括：第一散热基板; 第一引线框架，其通过图案化形成在所述第一散热基板上; 形成在所述第一引线框上的第一半导体器件; 堆叠在第一半导体器件上的第二半导体器件; 图案化并结合到第二半导体器件的第二引线框架; 以及形成在所述第一引线框架上的第二散热基板。

    Wafer level device package with sealing line having electroconductive pattern and method of packaging the same
    14.
    发明申请
    Wafer level device package with sealing line having electroconductive pattern and method of packaging the same 有权
    具有导电图案的密封线的晶片级器件封装及其封装方法

    公开(公告)号：US20080290479A1

    公开(公告)日：2008-11-27

    申请号：US12153705

    申请日：2008-05-22

    申请人： Ju Pyo Hong ,  Seog Moon Choi ,  Tae Hoon Kim ,  Job Ha ,  Seung Wook Park

    发明人： Ju Pyo Hong ,  Seog Moon Choi ,  Tae Hoon Kim ,  Job Ha ,  Seung Wook Park

    IPC分类号： H01L23/495 ,  H01L21/60

    CPC分类号： H01L21/50 ,  B81B2207/093 ,  B81C1/00301 ,  B81C2203/0118 ,  B81C2203/019 ,  H01L23/10 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/16195 ,  H01L2924/16235 ,  H03H9/1057 ,  H03H9/1071 ,  H01L2924/00

    摘要： Provided are wafer level package with a sealing line that seals a device and includes electroconductive patterns as an electrical connection structure for the device, and a method of packaging the same. In the wafer level package, a device substrate includes a device region, where a device is mounted, on the top surface. A sealing line includes a plurality of non-electroconductive patterns and a plurality of electroconductive patterns, and seals the device region. A cap substrate includes a plurality of vias respectively connected to the electroconductive patterns and is attached to the device substrate by the sealing line. Therefore, a simplified wafer level package structure that accomplishes electric connection through electroconductive patterns of a sealing line can be formed without providing an electrode pad for electric connection with a device.

    摘要翻译： 提供了具有密封设备并且包括作为设备的电连接结构的导电图案的密封线的晶片级封装以及其封装方法。 在晶片级封装中，器件衬底包括在顶表面上安装器件的器件区域。 密封线包括多个非导电图案和多个导电图案，并且密封该装置区域。 盖基板包括分别连接到导电图案的多个通孔，并通过密封线附接到器件基板。 因此，可以形成通过密封线的导电图案实现电连接的简化的晶片级封装结构，而不需要提供用于与器件电连接的电极焊盘。

    Heat radiating substrate and method of manufacturing the same
    16.
    发明申请
    Heat radiating substrate and method of manufacturing the same 审中-公开
    散热基板及其制造方法

    公开(公告)号：US20120085574A1

    公开(公告)日：2012-04-12

    申请号：US13064364

    申请日：2011-03-21

    申请人： Ji Hyun Park ,  Tae Hoon Kim ,  Sang Hyun Shin ,  Ki Ho Seo ,  Cheol Ho Heo ,  Young Ki Lee

    发明人： Ji Hyun Park ,  Tae Hoon Kim ,  Sang Hyun Shin ,  Ki Ho Seo ,  Cheol Ho Heo ,  Young Ki Lee

    IPC分类号： H05K1/14 ,  H05K3/42

    CPC分类号： H05K3/44 ,  H05K1/0203 ,  H05K1/053 ,  H05K3/202 ,  H05K3/4053 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2203/0315 ,  Y10T29/49165

    摘要： Provided are a heat radiating substrate and a method of manufacturing the same. The heat radiating substrate includes a substrate having a via-hole, an anode oxide layer formed on the entire surface of the substrate having the via-hole through an anodizing process, a first circuit pattern formed on the substrate on which the anode oxide layer is formed, and a second circuit pattern formed at a lower part of the via-hole to be connected to the via-hole. Therefore, it is possible to simplify a circuit forming process and readily manufacture the heat radiating substrate by applying a metal anodic bonding process, without using a conventional adhesion layer and metal seed when the heat radiating substrate is manufactured.

    摘要翻译： 提供一种散热基板及其制造方法。 散热基板包括具有通孔的基板，通过阳极氧化处理形成在具有通孔的基板的整个表面上的阳极氧化层，形成在基板上的阳极氧化物层为阳极氧化层 以及形成在通孔的下部以连接到通孔的第二电路图案。 因此，通过在制造散热基板时不使用常规的粘合层和金属种子，通过施加金属阳极接合工艺来简化电路形成工艺并容易地制造散热基板。

    Multilayered wiring substrate and manufacturing method thereof
    19.
    发明申请
    Multilayered wiring substrate and manufacturing method thereof 审中-公开
    多层布线基板及其制造方法

    公开(公告)号：US20110042130A1

    公开(公告)日：2011-02-24

    申请号：US12654529

    申请日：2009-12-22

    申请人： Chang Hyun Lim ,  Tae Hoon Kim ,  Young Ki Lee ,  Tae Hyun Kim ,  Ki Ho Seo

    发明人： Chang Hyun Lim ,  Tae Hoon Kim ,  Young Ki Lee ,  Tae Hyun Kim ,  Ki Ho Seo

    IPC分类号： H05K1/11 ,  H01K3/10 ,  H05K3/36

    CPC分类号： H05K3/4641 ,  H05K1/053 ,  H05K3/445 ,  H05K3/4623 ,  H05K2203/0315 ,  Y10T29/49126 ,  Y10T29/49162

    摘要： A multilayered wiring substrate and a manufacturing method thereof are disclosed. The multilayered wiring substrate includes: a stacked body including an insulating member and first and second metal cores stacked with the insulating member interposed therebetween, and having a through hole penetrating the first and second metal cores; first and second insulation layers formed on an external surface, excluding an inner wall of the through hole, of the first and second metal cores, respectively; first and second inner layer circuit patterns and first and second outer layer circuit patterns formed on the first and second insulation layers, respectively; first and second via electrodes electrically connecting the first and second inner layer circuit patterns and the first and second outer layer circuit patterns; a third insulation layer formed on the inner wall of the through hole; and a through electrode made of a conductive material filled in the through hole and electrically connecting the first and second outer layer circuit patterns.

    摘要翻译： 公开了一种多层布线基板及其制造方法。 所述多层布线基板包括：堆叠体，其包括绝缘部件和被插入其间的所述绝缘部件堆叠的第一和第二金属芯体，并且具有穿过所述第一和第二金属芯体的通孔; 第一和第二绝缘层分别形成在第一和第二金属芯的外表面上，不包括通孔的内壁; 分别形成在第一绝缘层和第二绝缘层上的第一和第二内层电路图案和第一和第二外层电路图案; 第一和第二通孔电极，电连接第一和第二内层电路图案以及第一和第二外层电路图案; 形成在所述通孔的内壁上的第三绝缘层; 以及由填充在所述通孔中的导电材料制成的电连接电连接所述第一外层电路图案和所述第二外层电路图案的贯通电极。

    Wafer level package and method of manufacturing the same
    20.
    发明申请
    Wafer level package and method of manufacturing the same 审中-公开
    晶圆级封装及其制造方法

    公开(公告)号：US20100193940A1

    公开(公告)日：2010-08-05

    申请号：US12382907

    申请日：2009-03-26

    申请人： Tae Hyun Kim ,  Tae Hoon Kim ,  Yun Pyo Kwak ,  Sung Keun Park ,  Jong Yeol Jeon

    发明人： Tae Hyun Kim ,  Tae Hoon Kim ,  Yun Pyo Kwak ,  Sung Keun Park ,  Jong Yeol Jeon

    IPC分类号： H01L23/02 ,  H01L21/52

    CPC分类号： H01L23/10 ,  H01L23/055 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/00

    摘要： The present invention relates to a wafer level package and a method of manufacturing the same. The wafer level package includes a first substrate including a first region and second regions with grooves around the first region; a semiconductor device positioned in the first region; first sealing members positioned in the grooves; a second substrate including projection units corresponding to the second regions in order to form a cavity corresponding to the first region; and second sealing members which are positioned above the projection units and laminate the first and second substrates to each other by being bonded to the first sealing members, and can prevent the sealing members from flowing to any region except for the sealing regions.

    摘要翻译： 本发明涉及一种晶片级封装及其制造方法。 晶片级封装包括包括第一区域的第一基板和围绕第一区域的凹槽的第二区域; 位于所述第一区域中的半导体器件; 位于凹槽中的第一密封构件; 第二基板，包括对应于第二区域的投影单元，以形成对应于第一区域的空腔; 以及第二密封构件，其位于投影单元的上方并且通过结合到第一密封构件将第一和第二基板彼此层合，并且可以防止密封构件流到除了密封区域之外的任何区域。