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    Multilayered wiring substrate and manufacturing method thereof
    1.
    发明申请
    Multilayered wiring substrate and manufacturing method thereof 审中-公开
    多层布线基板及其制造方法

    公开(公告)号：US20110042130A1

    公开(公告)日：2011-02-24

    申请号：US12654529

    申请日：2009-12-22

    申请人： Chang Hyun Lim ,  Tae Hoon Kim ,  Young Ki Lee ,  Tae Hyun Kim ,  Ki Ho Seo

    发明人： Chang Hyun Lim ,  Tae Hoon Kim ,  Young Ki Lee ,  Tae Hyun Kim ,  Ki Ho Seo

    IPC分类号： H05K1/11 ,  H01K3/10 ,  H05K3/36

    CPC分类号： H05K3/4641 ,  H05K1/053 ,  H05K3/445 ,  H05K3/4623 ,  H05K2203/0315 ,  Y10T29/49126 ,  Y10T29/49162

    摘要： A multilayered wiring substrate and a manufacturing method thereof are disclosed. The multilayered wiring substrate includes: a stacked body including an insulating member and first and second metal cores stacked with the insulating member interposed therebetween, and having a through hole penetrating the first and second metal cores; first and second insulation layers formed on an external surface, excluding an inner wall of the through hole, of the first and second metal cores, respectively; first and second inner layer circuit patterns and first and second outer layer circuit patterns formed on the first and second insulation layers, respectively; first and second via electrodes electrically connecting the first and second inner layer circuit patterns and the first and second outer layer circuit patterns; a third insulation layer formed on the inner wall of the through hole; and a through electrode made of a conductive material filled in the through hole and electrically connecting the first and second outer layer circuit patterns.

    摘要翻译： 公开了一种多层布线基板及其制造方法。 所述多层布线基板包括：堆叠体，其包括绝缘部件和被插入其间的所述绝缘部件堆叠的第一和第二金属芯体，并且具有穿过所述第一和第二金属芯体的通孔; 第一和第二绝缘层分别形成在第一和第二金属芯的外表面上，不包括通孔的内壁; 分别形成在第一绝缘层和第二绝缘层上的第一和第二内层电路图案和第一和第二外层电路图案; 第一和第二通孔电极，电连接第一和第二内层电路图案以及第一和第二外层电路图案; 形成在所述通孔的内壁上的第三绝缘层; 以及由填充在所述通孔中的导电材料制成的电连接电连接所述第一外层电路图案和所述第二外层电路图案的贯通电极。

    Wafer level package and method of manufacturing the same
    5.
    发明申请
    Wafer level package and method of manufacturing the same 审中-公开
    晶圆级封装及其制造方法

    公开(公告)号：US20100193940A1

    公开(公告)日：2010-08-05

    申请号：US12382907

    申请日：2009-03-26

    申请人： Tae Hyun Kim ,  Tae Hoon Kim ,  Yun Pyo Kwak ,  Sung Keun Park ,  Jong Yeol Jeon

    发明人： Tae Hyun Kim ,  Tae Hoon Kim ,  Yun Pyo Kwak ,  Sung Keun Park ,  Jong Yeol Jeon

    IPC分类号： H01L23/02 ,  H01L21/52

    CPC分类号： H01L23/10 ,  H01L23/055 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/00

    摘要： The present invention relates to a wafer level package and a method of manufacturing the same. The wafer level package includes a first substrate including a first region and second regions with grooves around the first region; a semiconductor device positioned in the first region; first sealing members positioned in the grooves; a second substrate including projection units corresponding to the second regions in order to form a cavity corresponding to the first region; and second sealing members which are positioned above the projection units and laminate the first and second substrates to each other by being bonded to the first sealing members, and can prevent the sealing members from flowing to any region except for the sealing regions.

    摘要翻译： 本发明涉及一种晶片级封装及其制造方法。 晶片级封装包括包括第一区域的第一基板和围绕第一区域的凹槽的第二区域; 位于所述第一区域中的半导体器件; 位于凹槽中的第一密封构件; 第二基板，包括对应于第二区域的投影单元，以形成对应于第一区域的空腔; 以及第二密封构件，其位于投影单元的上方并且通过结合到第一密封构件将第一和第二基板彼此层合，并且可以防止密封构件流到除了密封区域之外的任何区域。

    Substrate for light emitting diode package and light emitting diode package having the same
    6.
    发明申请
    Substrate for light emitting diode package and light emitting diode package having the same 审中-公开
    用于发光二极管封装的衬底和具有该发光二极管封装的发光二极管封装

    公开(公告)号：US20110042699A1

    公开(公告)日：2011-02-24

    申请号：US12654431

    申请日：2009-12-18

    申请人： Sung Keun Park ,  Seog Moon Choi ,  Young Ho Sohn ,  Tae Hyun Kim ,  Young Ki Lee

    发明人： Sung Keun Park ,  Seog Moon Choi ,  Young Ho Sohn ,  Tae Hyun Kim ,  Young Ki Lee

    IPC分类号： H01L33/00

    CPC分类号： H01L33/486 ,  H01L24/97 ,  H01L33/60 ,  H01L33/647 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4848 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48465

    摘要： A substrate for a light emitting diode (LED) package, and an LED package having the same are disclosed. The substrate for an LED package includes: a metal plate; an insulation oxide layer formed on a portion of the surface of the metal plate; a first conductive pattern formed at one region of the insulation oxide layer and providing a light emitting diode mounting area; and a second conductive pattern formed at another region of the insulation oxide layer such that it is separated from the first conductive pattern. In the substrate for an LED package, because regions of the insulation oxide layer other than regions for insulating conductive patterns are removed, heat generated from the light emitting diode can be effectively released. In addition, degradation of reflexibility and luminance of the LED due to the insulation oxide layer can be prevented.

    摘要翻译： 公开了一种用于发光二极管（LED）封装的衬底和具有该衬底的LED封装。 用于LED封装的衬底包括：金属板; 绝缘氧化物层，形成在所述金属板的所述表面的一部分上; 形成在所述绝缘氧化物层的一个区域并提供发光二极管安装区域的第一导电图案; 以及形成在所述绝缘氧化物层的另一区域处的第二导电图案，使得其与所述第一导电图案分离。 在LED封装用基板中，除去绝缘性导电图案以外的绝缘氧化物层的区域，能够有效地释放从发光二极管产生的热量。 此外，可以防止由于绝缘氧化物层导致的LED的反射性和亮度的劣化。

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开
    半导体封装

    公开(公告)号：US20140001611A1

    公开(公告)日：2014-01-02

    申请号：US13613797

    申请日：2012-09-13

    申请人： Eun Jung Jo ,  Jae Hyun Lim ,  Tae Hyun Kim ,  Young Ho Sohn

    发明人： Eun Jung Jo ,  Jae Hyun Lim ,  Tae Hyun Kim ,  Young Ho Sohn

    IPC分类号： H01L23/495

    CPC分类号： H01L23/49531 ,  H01L23/49537 ,  H01L23/49575 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49171 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/49111

    摘要： There is provided a semiconductor package capable of significantly reducing a size of a power semiconductor package including a power semiconductor device and a control device. The semiconductor package includes a lead frame including a first frame and a second frame; at least one first electronic device mounted on the first frame; a substrate engaged with the second frame and having one surface on which a wiring pattern is formed; and at least one second electronic device mounted on the substrate and electrically connected to the wiring pattern, a portion of the wiring pattern electrically connected to the at least one second electronic device being formed to have a line width smaller than an internal lead of the lead frame.

    摘要翻译： 提供了能够显着地减小包括功率半导体器件和控制装置的功率半导体封装的尺寸的半导体封装。 所述半导体封装包括引线框架，所述引线框架包括第一框架和第二框架; 安装在第一框架上的至少一个第一电子装置; 基板，与所述第二框架接合并且具有形成有布线图案的一个表面; 以及安装在所述基板上并电连接到所述布线图案的至少一个第二电子设备，所述布线图案的电连接到所述至少一个第二电子设备的部分形成为具有小于所述引线的内部引线的线宽 帧。

    Magnetic random access memory (MRAM) read with reduced disturb failure
    9.
    发明授权
    Magnetic random access memory (MRAM) read with reduced disturb failure 有权
    磁性随机存取存储器（MRAM）以减少的干扰故障读取

    公开(公告)号：US08570797B2

    公开(公告)日：2013-10-29

    申请号：US13035006

    申请日：2011-02-25

    申请人： Jung Pill Kim ,  Tae Hyun Kim ,  Kangho Lee

    发明人： Jung Pill Kim ,  Tae Hyun Kim ,  Kangho Lee

    IPC分类号： G11C11/14

    CPC分类号： G11C11/1673 ,  G11C11/1693

    摘要： Magnetic tunnel junctions (MTJs) in magnetic random access memory (MRAM) are subject to read disturb events when the current passing through the MTJ causes a spontaneous switching of the MTJ due to spin transfer torque (STT) from a parallel state to an anti-parallel state or from an anti-parallel state to a parallel state. Because the state of the MTJ corresponds to stored data, a read disturb event may cause data loss in MRAM devices. Read disturb events may be reduced by controlling the direction of current flow through the MTJ. For example, the current direction through a reference MTJ may be selected based on the state of the reference MTJ. In another example, the current direction through a data or reference MTJ may be alternated such that the MTJ is only subject to read disturb events during approximately half the read operations on the MTJ.

    摘要翻译： 磁流体随机存取存储器（MRAM）中的磁隧道结（MTJ）在经过MTJ的电流导致由于自旋转移转矩（STT）从平行状态到抗反射的MTJ自发切换时，受到读取干扰事件， 平行状态或从反平行状态到并行状态。 因为MTJ的状态对应于存储的数据，读取干扰事件可能导致MRAM设备中的数据丢失。 通过控制通过MTJ的电流的方向可以减少读取干扰事件。 例如，可以基于参考MTJ的状态来选择通过参考MTJ的当前方向。 在另一示例中，可以交替通过数据或参考MTJ的当前方向，使得MTJ仅在MTJ上的大约一半的读取操作期间经受读取干扰事件。

    Row-decoder circuit and method with dual power systems
    10.
    发明授权
    Row-decoder circuit and method with dual power systems 有权
    具有双电源系统的行解码器电路和方法

    公开(公告)号：US08526266B2

    公开(公告)日：2013-09-03

    申请号：US13032979

    申请日：2011-02-23

    申请人： Jung Pill Kim ,  Tae Hyun Kim ,  Seung H. Kang

    发明人： Jung Pill Kim ,  Tae Hyun Kim ,  Seung H. Kang

    IPC分类号： G11C8/00

    CPC分类号： G11C11/1653 ,  G11C8/08 ,  G11C8/10 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

    摘要： A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation.

    摘要翻译： 旋转转矩磁性随机存取存储器包括具有用于读取操作的电荷共享的双电压行解码器。 具有用于读取操作的电荷共享的双电压行解码器可降低读取干扰故障率，并提供强大的宏设计，提高产量。 在写入操作期间可以应用来自其中一个电源的电压。