公开(公告)号：US20130277844A1

公开(公告)日：2013-10-24

申请号：US13921032

申请日：2013-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chih CHIOU ,  Chen-Hua YU ,  Weng-Jin WU ,  Jung-Chih HU

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor component having a semiconductor substrate including an integrated circuit (IC) component, an interlayer dielectric (ILD) layer formed on the semiconductor substrate, a contact plug formed in the ILD layer and electrically connected to the IC component, a via plug formed in the ILD layer and extending through a portion of the semiconductor substrate, wherein the top surfaces of the ILD layer, the via plug and the contact plug are leveled off, and an interconnection structure comprising a plurality of metal layers formed in a plurality of inter-metal dielectric (IMD) layers, wherein a lowermost metal layer of the interconnection structure is electrically connected to the exposed portions of the contact plug and the via plug.

Abstract translation: 一种具有半导体衬底的半导体器件，包括集成电路（IC）部件，形成在半导体衬底上的层间电介质层（ILD）层，形成在ILD层中并与IC部件电连接的接触插塞，形成在 所述ILD层延伸穿过所述半导体衬底的一部分，其中所述ILD层，所述通孔插塞和所述接触插塞的顶表面被平整，以及包括形成在多个间隔层中的多个金属层的互连结构， 金属电介质（IMD）层，其中所述互连结构的最下面的金属层电连接到所述接触插塞和所述通孔塞的所述暴露部分。

公开(公告)号：US20130228927A1

公开(公告)日：2013-09-05

申请号：US13868140

申请日：2013-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Hua YU ,  Hai-Ching CHEN ,  Tien-I BAO

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L23/485 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76898 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.

Abstract translation: 半导体结构包括在衬底上的第一电介质层。 至少一个第一导电结构在第一介电层内。 第一导电结构包括在第一介电层的顶表面上方延伸的盖部分。 至少一个第一电介质间隔物位于第一导电结构的帽部分的至少一个侧壁上。

公开(公告)号：US20200286830A1

公开(公告)日：2020-09-10

申请号：US16883210

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie CHEN ,  Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chen-Hua YU

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20200266664A1

公开(公告)日：2020-08-20

申请号：US16867753

申请日：2020-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua YU ,  Hao-Yi TSAI ,  Tzu-Sung HUANG ,  Ming-Hung TSENG ,  Hung-Yi KUO

IPC: H02J50/10 ,  H01F38/14 ,  H04B5/00 ,  H02J7/00 ,  H01L23/64 ,  H01L23/538 ,  H01L23/522 ,  H01L23/498 ,  H01L23/31 ,  H01L23/10 ,  H01L21/3205 ,  H01F27/36

Abstract: A semiconductor device package is provided, including a semiconductor device, a molding material, and a conductive slot. The molding material surrounds the semiconductor device. The conductive slot is positioned over the molding material and having an opening and at least two channels connecting the opening to the edges of the conductive slot.

公开(公告)号：US20200091039A1

公开(公告)日：2020-03-19

申请号：US16373915

申请日：2019-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Liang SHAO ,  Wen-Lin SHIH ,  Su-Chun YANG ,  Chih-Hang TUNG ,  Chen-Hua YU

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00

Abstract: A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.

公开(公告)号：US20180151540A1

公开(公告)日：2018-05-31

申请号：US15362690

申请日：2016-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua YU ,  Jing-Cheng LIN ,  Po-Hao TSAI ,  An-Jhih SU

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L23/60

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L23/60 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film is electrically connected to the first ground bump.

公开(公告)号：US20170317023A1

公开(公告)日：2017-11-02

申请号：US15254135

申请日：2016-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua YU ,  Hao-Yi TSAI ,  Tzu-Sung HUANG ,  Ming-Hung TSENG ,  Hung-Yi KUO

IPC: H01L23/522 ,  H01L23/06 ,  H01L21/3205 ,  H01L21/56 ,  H02J7/02 ,  H01L23/31

CPC classification number: H02J7/025 ,  H01L21/32051 ,  H01L23/10 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/5227 ,  H01L23/5389 ,  H01L23/645 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2924/19042 ,  H01L2924/19105 ,  H02J7/0042 ,  H02J50/10 ,  H04B5/0037 ,  H04B5/0075

Abstract: A method for packaging a semiconductor device used in an electronic apparatus having wireless charging function is provided. The method includes coupling a semiconductor device and a coil over a redistribution layer. The method further includes forming a molding material over the semiconductor device and the coil. The method also includes forming a conductive metal slot over the molding material. An opening is formed on the conductive metal slot for allowing magnetic flux to pass through.

公开(公告)号：US20170141040A1

公开(公告)日：2017-05-18

申请号：US14941215

申请日：2015-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua YU ,  Wen-Chih CHIOU

IPC: H01L23/538 ,  H01L23/29 ,  H01L25/065 ,  H01L21/02 ,  H01L21/56 ,  H01L21/768 ,  H01L21/3105 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L21/02263 ,  H01L21/31051 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L25/0655 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/24137 ,  H01L2924/18162

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a polymer layer over the semiconductor die and the package layer. The chip package further includes a dielectric layer over the polymer layer. The dielectric layer is substantially made of a semiconductor oxide material. In addition, the chip package includes a conductive feature in the dielectric layer electrically connected to a conductive pad of the semiconductor die.

公开(公告)号：US20160190087A1

公开(公告)日：2016-06-30

申请号：US14584889

申请日：2014-12-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua YU ,  HsiaoYun LO ,  Yi-Hsiu CHEN ,  Wen-Chih CHIOU

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L2224/7501 ,  H01L2224/75304 ,  H01L2224/75305 ,  H01L2224/75313 ,  H01L2224/75315 ,  H01L2224/75318 ,  H01L2224/7565 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/8013 ,  H01L2224/80132

Abstract: A chip-stacking apparatus for stacking a chip on a substrate is provided. The chip-stacking apparatus includes a substrate support configured to carry the substrate and a transport device configured to dispose a chip to the substrate. The transport device includes a bond head including a bond base and an attaching element disposed on the bond base and configured to allow the chip to be attached thereon. The center area of the attaching element is higher than an edge area of the attaching element relative to the bond base.

Abstract translation: 提供了一种用于在基板上堆叠芯片的芯片堆叠装置。 芯片堆叠装置包括被配置为承载基板的基板支撑件和配置成将芯片配置到基板的输送装置。 输送装置包括：接合头，其包括接合基底和设置在接合基底上并被配置为允许芯片附接在其上的附接元件。 附着元件的中心区域比附着元件相对于接合基座的边缘区域高。

公开(公告)号：US20150102472A1

公开(公告)日：2015-04-16

申请号：US14050628

申请日：2013-10-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Hao TSAI ,  Wei-Chih LAI ,  Chuei-Tang WANG ,  Chen-Hua YU

IPC: H01L23/552 ,  H01L23/532 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L23/552 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/5225 ,  H01L23/525 ,  H01L23/5329 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a passivation layer, a protective layer, a post-passivation interconnect (PPI) structure, and a shielding layer. The semiconductor substrate has electrical circuitry. The dielectric layer is formed on the semiconductor substrate. The passivation layer is formed on the dielectric layer. The first protective layer is formed on the passivation layer. The PPI structure is disposed on the first protective layer and has a signal line and a ground line. The shielding layer is disposed over the semiconductor substrate and between the signal line and the electrical circuitry. The shielding layer is substantially equi-potentially connected to the ground line of the PPI structure.

Abstract translation: 半导体器件包括半导体衬底，电介质层，钝化层，保护层，钝化后互连（PPI）结构和屏蔽层。 半导体衬底具有电路。 介电层形成在半导体衬底上。 钝化层形成在电介质层上。 第一保护层形成在钝化层上。 PPI结构设置在第一保护层上，并具有信号线和接地线。 屏蔽层设置在半导体衬底之上并且在信号线和电路之间。 屏蔽层基本上等同地连接到PPI结构的接地线。