公开(公告)号：US20240079324A1

公开(公告)日：2024-03-07

申请号：US18503947

申请日：2023-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie CHEN ,  Ying-Ju CHEN ,  Chen-Hua YU ,  Der-Chyang YEH ,  Hsien-Wei CHEN

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16235 ,  H01L2224/24147 ,  H01L2224/25171 ,  H01L2224/73209 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20210351130A1

公开(公告)日：2021-11-11

申请号：US17366575

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jie CHEN ,  Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chen-Hua YU

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20170317057A1

公开(公告)日：2017-11-02

申请号：US15227870

申请日：2016-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ying-Ju CHEN ,  Jie CHEN ,  Hsien-Wei CHEN

IPC: H01L25/065 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L22/20 ,  H01L23/3142 ,  H01L23/481 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/15311

Abstract: A method of forming a semiconductor device includes the following operations: (i) receiving a precursor package including a precursor substrate and a plurality of semiconductor packages on the precursor substrate, in which a gap is presented between the precursor substrate and each of the semiconductor packages; (ii) forming underfill material filling the gaps; (iii) cutting the precursor substrate along a region between adjacent ones of the semiconductor packages to form a plurality of discrete package-on-package devices; and (iv) applying supplemental underfill material to one of the package-on-package devices.

公开(公告)号：US20150137352A1

公开(公告)日：2015-05-21

申请号：US14082997

申请日：2013-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju CHEN ,  Hsien-Wei CHEN

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05569 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/11 ,  H01L2224/11334 ,  H01L2224/11826 ,  H01L2224/1191 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13681 ,  H01L2224/13686 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/04953 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/04941 ,  H01L2924/01047

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.

Abstract translation: 提供了用于形成半导体器件的机构的实施例。 半导体器件包括衬底上的接触焊盘。 半导体器件还包括在衬底上的钝化层和接触焊盘的第一部分，并且接触焊盘的第二部分通过开口暴露。 半导体器件还包括钝化层上的钝化后互连层并且耦合到接触焊盘的第二部分。 此外，半导体器件包括在钝化后互连层上方的凸起并且在开口外部。 该半导体器件还包括扩散阻挡层，其将突起与钝化后互连层物理绝缘，同时将凸块电连接到后钝化互连层。

公开(公告)号：US20200286830A1

公开(公告)日：2020-09-10

申请号：US16883210

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie CHEN ,  Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chen-Hua YU

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.