公开(公告)号：US20180350774A1

公开(公告)日：2018-12-06

申请号：US15609743

申请日：2017-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie CHEN ,  Hsien-Wei CHEN

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protective layer surrounding the semiconductor die. The chip package also includes an interface between the semiconductor die and the protective layer. The chip package further includes a conductive layer over the protective layer and the semiconductor die, and the conductive layer has a first portion and a second portion. The first portion is closer to an inner portion of the semiconductor die than the second portion. The first portion is in direct contact with the second portion. The second portion extends across the interface, and the second portion has a line width greater than that of the first portion.

公开(公告)号：US20170025371A1

公开(公告)日：2017-01-26

申请号：US15194160

申请日：2016-06-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jie CHEN ,  Hsien-Wei CHEN

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/768 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/525 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02255 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0382 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/11015 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/05994 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformity deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A semiconductor device with bum stop structure is also provided.

Abstract translation: 提供一种半导体器件的制造方法。 在该方法中，在金属化层中形成导电焊盘和金属突起图案。 钝化层被共形沉积在金属化之上，并且保护层在钝化层上沉积。 此外，钝化后互连结构（PPI）保形地形成在保护层上，并且PPI结构包括着陆焊盘区域，在着陆焊盘区域的至少一部分上的突出图案以及电连接到 导电垫。 然后将焊料凸块放置在与PPI结构的突出图案接触的着陆焊盘区域上。 还提供了具有烧结停止结构的半导体器件。

公开(公告)号：US20150214170A1

公开(公告)日：2015-07-30

申请号：US14166531

申请日：2014-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jie CHEN ,  Hsien-Wei CHEN

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L24/13 ,  H01L21/768 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/485 ,  H01L23/525 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02255 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0382 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/10145 ,  H01L2224/11015 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/05994 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/2064 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformally deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A to semiconductor device with bum stop structure is also provided.

Abstract translation: 提供一种半导体器件的制造方法。 在该方法中，在金属化层中形成导电焊盘和金属突起图案。 钝化层在金属化之上共形沉积，保护层共形沉积在钝化层上。 此外，钝化后互连结构（PPI）保形地形成在保护层上，并且PPI结构包括着陆焊盘区域，在着陆焊盘区域的至少一部分上的突出图案以及电连接到 导电垫。 然后将焊料凸块放置在与PPI结构的突出图案接触的着陆焊盘区域上。 还提供了具有烧结停止结构的半导体器件。

公开(公告)号：US20210351130A1

公开(公告)日：2021-11-11

申请号：US17366575

申请日：2021-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Jie CHEN ,  Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chen-Hua YU

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20180158777A1

公开(公告)日：2018-06-07

申请号：US15684224

申请日：2017-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie CHEN ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L24/02 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0233 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/24147 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73209 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: An integrated circuit (IC) package with improved performance and reliability is disclosed. The IC package includes an IC die and a routing structure. The IC die includes a conductive via having a peripheral edge. The routing structure includes a conductive structure coupled to the conductive via. The conductive structure may include a cap region, a routing region, and an intermediate region. The cap region may overlap an area of the conductive via. The routing region may have a first width and the intermediate region may have a second width along the peripheral edge of the conductive via, where the second width may be greater than the first width.

公开(公告)号：US20160322238A1

公开(公告)日：2016-11-03

申请号：US14698694

申请日：2015-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsien-Wei CHEN ,  Jie CHEN

IPC: H01L21/56 ,  H01L21/683 ,  H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A method of forming a molding layer includes the following operations: forming a substrate having at least one column structure thereon; flipping over the substrate having the column structure such that the column structure is beneath the substrate; dipping the column structure of the flipped substrate into a molding material fluid contained in a container; and separating the column structure of the flipped substrate from the container to form a molding layer covering and in contact with the column structure.

Abstract translation: 形成模塑层的方法包括以下操作：在其上形成至少一个柱结构的基板; 翻转在具有柱结构的衬底上，使得柱结构在衬底下方; 将翻转的基板的柱结构浸入容纳在容器中的成型材料流体中; 并将翻转的基板的柱结构与容器分离以形成覆盖并与柱结构接触的成型层。

公开(公告)号：US20180151499A1

公开(公告)日：2018-05-31

申请号：US15498254

申请日：2017-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie CHEN ,  Hsien-Wei CHEN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/46 ,  H01L2224/04042 ,  H01L2224/05015 ,  H01L2224/08054 ,  H01L2224/08056 ,  H01L2224/4807 ,  H01L2224/4846

Abstract: Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and coupled to the through-via, and a second RDL wire disposed on the second surface of the molding material and parallel to the first RDL wire. The second surface is opposite to the first surface. A portion of the second RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.

公开(公告)号：US20180012843A1

公开(公告)日：2018-01-11

申请号：US15205229

申请日：2016-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie CHEN ,  Hsien-Wei CHEN

IPC: H01L23/538

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Package structures are provided. The package structure includes an integrated circuit die. The package structure also includes a package layer surrounding the integrated circuit die. There is an interface between the integrated circuit die and the package layer. The package structure further includes a redistribution structure below the integrated circuit die and the package layer. The redistribution structure includes active conductive lines electrically connected to the integrated circuit die. The redistribution structure also includes a dummy conductive line between the active conductive lines. The dummy conductive line extends across the interface.

公开(公告)号：US20170317057A1

公开(公告)日：2017-11-02

申请号：US15227870

申请日：2016-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ying-Ju CHEN ,  Jie CHEN ,  Hsien-Wei CHEN

IPC: H01L25/065 ,  H01L21/78 ,  H01L21/66 ,  H01L23/48 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L22/20 ,  H01L23/3142 ,  H01L23/481 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/15311

Abstract: A method of forming a semiconductor device includes the following operations: (i) receiving a precursor package including a precursor substrate and a plurality of semiconductor packages on the precursor substrate, in which a gap is presented between the precursor substrate and each of the semiconductor packages; (ii) forming underfill material filling the gaps; (iii) cutting the precursor substrate along a region between adjacent ones of the semiconductor packages to form a plurality of discrete package-on-package devices; and (iv) applying supplemental underfill material to one of the package-on-package devices.

公开(公告)号：US20200286830A1

公开(公告)日：2020-09-10

申请号：US16883210

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie CHEN ,  Ying-Ju CHEN ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chen-Hua YU

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.