公开(公告)号：US20220357652A1

公开(公告)日：2022-11-10

申请号：US17874676

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peter Yu ,  Chih-Tung Hsu ,  Kevin Wang ,  Chih-Chia Hu ,  Roger Chen

IPC: G03F1/70 ,  G03F1/42 ,  G03F1/38

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

公开(公告)号：US20210082779A1

公开(公告)日：2021-03-18

申请号：US16572612

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Chih-Chia Hu

IPC: H01L23/10 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

Abstract: Semiconductor packages are disclosed. A semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. A first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring.

公开(公告)号：US20200343218A1

公开(公告)日：2020-10-29

申请号：US16398159

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes an integrated circuit structure, a first die stack and a dummy die. The first die stack includes a plurality of first die structures and is bonded to the integrated circuit structure at a first side of the first die stack. The dummy die includes a plurality of through substrate vias, is located aside the first die stack and is electrically connected to the integrated circuit structure at the first side of the first die stack. In some embodiments, the height of the through substrate vias of the dummy die is the same as the height of the first die stack.

公开(公告)号：US20200050102A1

公开(公告)日：2020-02-13

申请号：US16658909

申请日：2019-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peter Yu ,  Chih-Tung Hsu ,  Kevin Wang ,  Chih-Chia Hu ,  Roger Chen

IPC: G03F1/70 ,  G03F1/38 ,  G03F1/00 ,  G03F1/42

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

公开(公告)号：US11916031B2

公开(公告)日：2024-02-27

申请号：US17745225

申请日：2022-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Ching-Pin Yuan ,  Sung-Feng Yeh ,  Sen-Bor Jan ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L23/544 ,  H01L25/065 ,  H01L23/522

CPC classification number: H01L24/06 ,  H01L23/522 ,  H01L23/544 ,  H01L24/05 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/0612 ,  H01L2224/06051 ,  H01L2224/06132 ,  H01L2224/08121 ,  H01L2224/08145 ,  H01L2224/091 ,  H01L2224/0913 ,  H01L2224/09051 ,  H01L2224/8001 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80203 ,  H01L2224/80357 ,  H01L2224/80815 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/80986 ,  H01L2924/3511 ,  H01L2224/091 ,  H01L2924/00012 ,  H01L2224/05555 ,  H01L2924/00012 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.

公开(公告)号：US20230275031A1

公开(公告)日：2023-08-31

申请号：US17661325

申请日：2022-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Sung-Feng Yeh ,  Ming-Fa Chen

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/544 ,  H01L23/562 ,  H01L23/481 ,  H01L2223/54426

Abstract: A method includes bonding a first plurality of active dies to a second plurality of active dies in a wafer. The second plurality of active dies are in an inner region of the wafer. A first plurality of dummy dies are bonded to a second plurality of dummy dies in the wafer. The second plurality of dummy dies are in a peripheral region of the wafer, and the peripheral region encircles the inner region.

公开(公告)号：US20230260941A1

公开(公告)日：2023-08-17

申请号：US17663328

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Yu-Hsiung Wang ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L24/08 ,  H01L24/80 ,  H01L24/03 ,  H01L24/05 ,  H01L23/5226 ,  H01L23/5283 ,  H01L21/7684 ,  H01L21/76898 ,  H01L21/76816 ,  H01L21/76807 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08237 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/05647 ,  H01L2224/05546 ,  H01L2224/05573 ,  H01L2224/05006 ,  H01L2224/05008 ,  H01L2224/05082 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381

Abstract: An embodiment is a method including forming a first interconnect structure over a first substrate, forming a redistribution via over the first interconnect structure, the redistribution via being electrically coupled to at least one of the metallization patterns of the first interconnect structure, forming a redistribution pad over the redistribution via, the redistribution pad being electrically coupled to the redistribution via, forming a first dielectric layer over the redistribution pad, and forming a second dielectric layer over the first dielectric layer. The method also includes patterning the first and second dielectric layers, forming a bond via over the redistribution pad and in the first dielectric layer, the bonding via being electrically coupled to the redistribution pad, the bond via overlapping the redistribution via, and forming a first bond pad over the bonding via and in the second dielectric layer, the first bond pad being electrically coupled to the bond via.

公开(公告)号：US20210255540A1

公开(公告)日：2021-08-19

申请号：US17306684

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Peter Yu ,  Chih-Tung Hsu ,  Kevin Wang ,  Chih-Chia Hu ,  Roger Chen

IPC: G03F1/70 ,  G03F1/42 ,  G03F1/38

Abstract: Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

公开(公告)号：US11088041B2

公开(公告)日：2021-08-10

申请号：US16572612

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Chih-Chia Hu

IPC: H01L23/34 ,  H01L23/48 ,  H01L21/4763 ,  H01L23/10 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L23/522

Abstract: Semiconductor packages are disclosed. A semiconductor package includes an integrated circuit, a first die and a second die. The first die includes a first bonding structure and a first seal ring. The first bonding structure is bonded to the integrated circuit and disposed at a first side of the first die. The second die includes a second bonding structure. The second bonding structure is bonded to the integrated circuit and disposed at a first side of the second die. The first side of the first die faces the first side of the second die. A first portion of the first seal ring is disposed between the first side and the first bonding structure, and a width of the first portion is smaller than a width of a second portion of the first seal ring.

公开(公告)号：US11080455B1

公开(公告)日：2021-08-03

申请号：US16924195

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chia Hu ,  Ming-Fa Chen ,  Sen-Bor Jan ,  Meng-Wei Chiang

IPC: G06F30/392 ,  H01L23/48 ,  G06F119/06 ,  H01L27/088 ,  H01L29/06

Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.