公开(公告)号：US10861692B2

公开(公告)日：2020-12-08

申请号：US15794352

申请日：2017-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Ti Wang ,  Chih-Wei Lin ,  Fu-Hsien Li ,  Yi-Ming Chen ,  Cheng-Ho Hung

IPC: H01L21/02 ,  G01N33/00 ,  B23P6/00 ,  H01L21/66 ,  G01B11/24 ,  H01L21/673 ,  H01L21/677 ,  B25J18/00 ,  B25J1/04

Abstract: A method includes receiving a carrier with a plurality of wafers inside; supplying a purge gas to an inlet of the carrier; extracting an exhaust gas from an outlet of the carrier; and generating a health indicator of the carrier while performing the supplying of the purge gas and the extracting of the exhaust gas.

公开(公告)号：US20200258801A1

公开(公告)日：2020-08-13

申请号：US16858737

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Cheng Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/367 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.

公开(公告)号：US20190333870A1

公开(公告)日：2019-10-31

申请号：US15964091

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Tse Chen ,  Ching-Hua Hsieh ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Hao-Cheng Hou ,  Jung-Wei Cheng

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/02 ,  H01L21/48

Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.

公开(公告)号：US20190304939A1

公开(公告)日：2019-10-03

申请号：US15937339

申请日：2018-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih Wei Bih ,  Sheng-Wei Yeh ,  Yen-Yu Chen ,  Wen-Hao Cheng ,  Chih-Wei Lin ,  Chun-Chih Lin

IPC: H01L23/00 ,  H01L21/02

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

公开(公告)号：US10157846B2

公开(公告)日：2018-12-18

申请号：US15292762

申请日：2016-10-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shing-Chao Chen ,  Chih-Wei Lin ,  Tsung-Hsien Chiang ,  Ming-Da Cheng ,  Ching-Hua Hsieh

IPC: H01L21/44 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

Abstract: Structures and formation methods of a chip package are provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes cutting an upper portion of the dielectric layer to improve flatness of the dielectric layer. In addition, the method includes forming a conductive layer over the dielectric layer after cutting the upper portion of the dielectric layer.

公开(公告)号：US20180337149A1

公开(公告)日：2018-11-22

申请号：US15599480

申请日：2017-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Shing-Chao Chen ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Meng-Tse Chen ,  Sheng-Hsiang Chiu ,  Sheng-Feng Weng

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L2224/05008

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.

公开(公告)号：US10043802B2

公开(公告)日：2018-08-07

申请号：US14689859

申请日：2015-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo ,  Cheng-Wei Lian

IPC: H01L27/092 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/40 ,  H01L21/28 ,  H01L21/8238

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The gate structure includes a gate dielectric layer formed over the substrate and a capping layer formed over the gate dielectric layer. The gate structure further includes a capping oxide layer formed over the capping layer and a work function metal layer formed over the capping oxide layer. The gate structure further includes a gate electrode layer formed over the work function metal layer.

公开(公告)号：US09837487B2

公开(公告)日：2017-12-05

申请号：US14954524

申请日：2015-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0607 ,  H01L21/28264 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20240379740A1

公开(公告)日：2024-11-14

申请号：US18781290

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Lin ,  Chih-Lin Wang ,  Kang-Min Kuo

IPC: H01L29/06 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

公开(公告)号：US20240234210A1

公开(公告)日：2024-07-11

申请号：US18151643

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chun Liao ,  Yen-Hung Chen ,  Ching-Hua Hsieh ,  Sung-Yueh Wu ,  Chih-Wei Lin ,  Kung-Chen Yeh

IPC: H01L21/822 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L21/822 ,  H01L21/3065 ,  H01L21/56 ,  H01L23/3121 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/08059 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/10156 ,  H01L2924/10157

Abstract: An integrated circuit package including integrated circuit dies and a method of forming are provided. The integrated circuit package may include a first integrated circuit die and a second integrated circuit die bonded to the first integrated circuit die. The first integrated circuit die may include a first substrate, a first interconnect structure, and a first bonding layer. The first interconnect structure may be between the first bonding layer and the first substrate. The second integrated circuit die may include a second substrate, a second interconnect structure, and a second bonding layer. The second interconnect structure may be between the second bonding layer and the second substrate. A first surface of the first bonding layer may be in direct contact with a first surface of the second bonding layer. A sidewall the first bonding layer and the first surface of the second bonding layer may form a first acute angle.