公开(公告)号：US20190096848A1

公开(公告)日：2019-03-28

申请号：US15935309

申请日：2018-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Kuan-Liang Liu ,  Kuo Liang Lu ,  Ping-Yin Liu

IPC: H01L23/00 ,  B23K37/04

Abstract: An apparatus and method is provided for controlling a propagation of a bond wave during semiconductor processing. The apparatus has a first chuck to selectively retain a first workpiece. A second chuck selectively retains a second workpiece. The first and second chucks selectively secure at least a periphery of the respective first workpiece and second workpiece. An air vacuum is circumferentially located in a region between the first chuck and second chuck. The air vacuum is configured to induce a vacuum between the first workpiece and second workpiece to selectively bring the first workpiece and second workpiece together from a propagation point. The air vacuum can be localized air vacuum guns, a vacuum disk, or an air curtain positioned about the periphery of the region between the first chuck and second chuck. The air curtain induces a lower pressure within the region between the first and second chucks.

公开(公告)号：US20180059534A1

公开(公告)日：2018-03-01

申请号：US15356204

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Tu ,  Chun-Lang Chen ,  Chue San Yoo ,  Jong-Yuh Chang ,  Chia-Shiung Tsai ,  Ping-Yin Liu ,  Hsin-Chang Lee ,  Chih-Cheng Lin ,  Yun-Yue Lin

IPC: G03F1/62 ,  H01L21/033

CPC classification number: G03F1/62 ,  C23C14/16 ,  C23C14/165 ,  C23C14/18 ,  C23C16/01 ,  C23C16/26 ,  C23C16/56 ,  C23C28/32 ,  G03F1/64 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.

公开(公告)号：US11742321B2

公开(公告)日：2023-08-29

申请号：US17319558

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Kuan-Liang Liu ,  Kuo Liang Lu ,  Ping-Yin Liu

IPC: B23K37/00 ,  H01L23/00 ,  B23K37/04 ,  H01L21/683 ,  H01L21/67 ,  H01L21/20 ,  H01L21/762 ,  B23K101/40

CPC classification number: H01L24/94 ,  B23K37/04 ,  B23K37/0408 ,  H01L21/2007 ,  H01L21/67092 ,  H01L21/6831 ,  H01L21/6838 ,  H01L21/76251 ,  H01L24/75 ,  H01L24/83 ,  B23K2101/40 ,  H01L2224/753 ,  H01L2224/759 ,  H01L2224/75704 ,  H01L2224/75724 ,  H01L2224/75744 ,  H01L2224/83209 ,  H01L2224/83894 ,  H01L2224/83908 ,  H01L2924/1203 ,  H01L2924/12043 ,  H01L2924/1304 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/00012 ,  H01L2924/12043 ,  H01L2924/00012 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/1461 ,  H01L2924/00012

Abstract: The present disclosure, in some embodiments, relates to a workpiece bonding apparatus. The workpieces bonding apparatus includes a first substrate holder having a first surface configured to receive a first workpiece, and a second substrate holder having a second surface configured to receive a second workpiece. A vacuum apparatus is positioned between the first substrate holder and the second substrate holder and is configured to selectively induce a vacuum between the first surface and the second surface. The vacuum is configured to attract the first surface and the second surface toward one another.

公开(公告)号：US11721637B2

公开(公告)日：2023-08-08

申请号：US16884437

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Ping-Yin Liu

IPC: H01L23/544 ,  H01L23/00 ,  B23Q17/22 ,  H01L21/18 ,  H01L21/68

CPC classification number: H01L23/544 ,  H01L24/83 ,  B23Q17/22 ,  H01L21/187 ,  H01L21/681 ,  H01L2223/54426 ,  H01L2224/8313

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.

公开(公告)号：US20210273167A1

公开(公告)日：2021-09-02

申请号：US16806064

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Liu ,  Chia-Shiung Tsai ,  Xin-Hua Huang ,  Yu-Hsing Chang ,  Yeong-Jyh Lin

IPC: H01L51/00 ,  H01L51/50 ,  H01L51/56 ,  C23C16/458 ,  C23C16/04

Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.

公开(公告)号：US20200064730A1

公开(公告)日：2020-02-27

申请号：US16666679

申请日：2019-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Liu ,  Chang-Ming Wu ,  Chia-Shiung Tsai ,  Xin-Hua Huang

IPC: G03F1/64 ,  G03F1/62 ,  G03F7/20

Abstract: A method for forming a pellicle apparatus involves forming a device substrate by depositing one or more pellicle layers defined over a base device layer, where a release layer is formed thereover. An adhesive layer is formed over a transparent carrier substrate. The adhesive layer is bonded to the release layer, defining a composite substrate comprised of the device and carrier substrates. The base device layer is removed from the composite structure and a pellicle frame is attached to an outermost one of the pellicle layers. A pellicle region is isolated from a remainder of the composite structure, and an ablation of the release layer is performed through the transparent carrier substrate, defining the pellicle apparatus comprising a pellicle film attached to the pellicle frame. The pellicle apparatus is then from a remaining portion of the composite substrate.

公开(公告)号：US10509312B2

公开(公告)日：2019-12-17

申请号：US16013163

申请日：2018-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Liu ,  Chang-Ming Wu ,  Chia-Shiung Tsai ,  Xin-Hua Huang

IPC: G03F7/20 ,  G03F1/64

Abstract: A method for forming a pellicle apparatus involves forming a device substrate by depositing one or more pellicle layers defined over a base device layer, where a release layer is formed thereover. An adhesive layer is formed over a transparent carrier substrate. The adhesive layer is bonded to the release layer, defining a composite substrate comprised of the device and carrier substrates. The base device layer is removed from the composite structure and a pellicle frame is attached to an outermost one of the pellicle layers. A pellicle region is isolated from a remainder of the composite structure, and an ablation of the release layer is performed through the transparent carrier substrate, defining the pellicle apparatus comprising a pellicle film attached to the pellicle frame. The pellicle apparatus is then from a remaining portion of the composite substrate.

公开(公告)号：US20190092627A1

公开(公告)日：2019-03-28

申请号：US15855449

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Hua Lin ,  Chang-Ming Wu ,  Chung-Yi Yu ,  Ping-Yin Liu ,  Jung-Huei Peng

IPC: B81C1/00 ,  B81B7/00 ,  H01L23/00

Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

公开(公告)号：US11854795B2

公开(公告)日：2023-12-26

申请号：US17655638

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Ping-Yin Liu ,  Hung-Hua Lin ,  Hsun-Chung Kuang ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: B23K1/00 ,  H01L21/02 ,  B23K1/20 ,  B23K20/02 ,  B23K20/233 ,  B23K20/24 ,  H01L23/00 ,  B23K101/40 ,  B23K101/42

CPC classification number: H01L21/02068 ,  B23K1/0016 ,  B23K1/206 ,  B23K20/026 ,  B23K20/233 ,  B23K20/24 ,  H01L24/89 ,  B23K2101/40 ,  B23K2101/42 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986

Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

公开(公告)号：US20220216052A1

公开(公告)日：2022-07-07

申请号：US17655638

申请日：2022-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xin-Hua Huang ,  Ping-Yin Liu ,  Hung-Hua Lin ,  Hsun-Chung Kuang ,  Yuan-Chih Hsieh ,  Lan-Lin Chao ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L21/02 ,  B23K1/20 ,  B23K1/00 ,  B23K20/02 ,  B23K20/233 ,  B23K20/24 ,  H01L23/00

Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.